or3l165b Lattice Semiconductor Corp., or3l165b Datasheet - Page 31

• Manufacturer Part Number: or3l165b
• Description: Orca Or3lxxxb Series Field-programmable Gate Arrays
• Manufacturer: Lattice Semiconductor Corp.

Data Addendum
March 2002
Lattice Semiconductor
Timing Characteristics
Table 19. OR3Lxxx Input to ExpressCLK (ECLK) Fast-Capture Setup/Hold Time (Pin-to-Pin) (continued)
OR3LxxB Commercial: V
to 3.6 V, V
Notes:
The pin-to-pin timing parameters in this table should be used instead of results reported by ORCA Foundry.
The ECLK delays are to all of the PIOs on one side of the device for middle pin input, or two sides of the device
for corner pin input. The delay includes both the input buffer delay and the clock routing to the PIO clock input.
Input to ECLK Hold Time
(corner ECLK pin)
Input to ECLK Hold Time
(corner ECLK pin, delayed data input)
(T
J
= 85 °C, V
DD
2 = 2.38 V to 2.63 V, –40 °C
Description
DD
= min, V
DD
DD
= 3.0 V to 3.6 V, V
2 = min)
Figure 9. Input to ExpressCLK Setup/Hold Time
(continued)
INPUT
CLK
OR3L165
OR3L225
OR3L165
OR3L225
<
Device
T
A
DD
<
+85 °C.
2 = 2.38 V to 2.63 V, 0 °C
CLKCNTRL
Min
0.0
0.0
0.0
0.0
-7
ECLK
Max
PIO ECLK LATCH
—
—
—
—
D
Min
0.0
0.0
0.0
0.0
Q
ORCA OR3LxxxB Series FPGAs
-8
<
T
Max
A
—
—
—
—
<
70 °C; Industrial: V
Unit
ns
ns
ns
ns
DD
= 3.0 V
5-4847(F).b
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