or3l165b Lattice Semiconductor Corp., or3l165b Datasheet - Page 30
or3l165b
Manufacturer Part Number
or3l165b
Description
Orca Or3lxxxb Series Field-programmable Gate Arrays
Manufacturer
Lattice Semiconductor Corp.
Datasheet
1.OR3L165B.pdf
(88 pages)
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ORCA OR3LxxxB Series FPGAs
Timing Characteristics
Table 19. OR3Lxxx Input to ExpressCLK (ECLK) Fast-Capture Setup/Hold Time (Pin-to-Pin)
OR3LxxB Commercial: V
to 3.6 V, V
Notes:
The pin-to-pin timing parameters in this table should be used instead of results reported by ORCA Foundry.
The ECLK delays are to all of the PIOs on one side of the device for middle pin input, or two sides of the
device for corner pin input. The delay includes both the input buffer delay and the clock routing to the PIO
clock input.
30
Input to ECLK Setup Time
(middle ECLK pin)
Input to ECLK Setup Time
(middle ECLK pin, delayed data input)
Input to ECLK Setup Time
(corner ECLK pin)
Input to ECLK Setup Time
(corner ECLK pin, delayed data input)
Input to ECLK Hold Time
(middle ECLK pin)
Input to ECLK Hold Time
(middle ECLK pin, delayed data input)
(T
J
= 85 °C, V
DD
2 = 2.38 V to 2.63 V, –40 °C
Description
DD
= min, V
DD
DD
= 3.0 V to 3.6 V, V
2 = min)
(continued)
OR3L165
OR3L225
OR3L165
OR3L225
OR3L165
OR3L225
OR3L165
OR3L225
OR3L165
OR3L225
OR3L165
OR3L225
<
Device
T
A
DD
<
+85 °C.
2 = 2.38 V to 2.63 V, 0 °C
12.62
12.60
10.33
10.13
2.63
2.61
Min
0.0
0.0
0.0
0.0
0.0
0.0
-7
Max
—
—
—
—
—
—
—
—
—
—
—
—
0.96
0.95
9.97
9.96
8.09
7.93
Min
0.0
0.0
0.0
0.0
0.0
0.0
-8
<
T
Max
—
—
—
—
—
—
—
—
—
—
—
—
A
<
70 °C; Industrial: V
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Lattice Semiconductor
Data Addendum
March 2002
DD
= 3.0 V