hy5ps1g821m Hynix Semiconductor, hy5ps1g821m Datasheet - Page 17

• Manufacturer Part Number: hy5ps1g821m
• Description: 1gb Ddr2 Sdram
• Manufacturer: Hynix Semiconductor

Rev. 0.2 / Oct. 2005
EMRS(2)
The extended mode register(2) controls refresh related features. The default value of the extended mode reg-
ister(2) is not defined, therefore the extended mode register(2) must be written after power-up for proper
operation. The extended mode register(2) is written by asserting low on /CS,/RAS,/CAS,/WE, high on BA1
and low on BA0, while controling the states of address pins A0~A15. The DDR2 SDRAM should be in all bank
precharge with CKE already high prior to writing into the extended mode register(2). Mode register contents
can be changed using the same command and clock cycle requirements during normal operation as long as
all bank are in the precharge state.
EMRS(2) Programming:
*1 : The rest bits in EMRS(2) is reserved for future use and all bits except A7, BA0 and BA1 must be
programmed to 0 when setting the mode register during initialization.
Due to the migration natural, user needs to ensure the DRAM part supports higher than 85℃ Tcase tempera-
ture self-refresh entry. JEDEC standard DDR2 SDRAM Module user can look at DDR2 SDRAM Module SPD
fileld Byte 49 bit[0]. If the high temperature self-refresh mode is supported then controller can set the EMRS2
[A7] bit to enable the self-refresh rate in case of higher than 85℃ temperature self-refresh operation. For the
lose part user, please refer to the Hynix web site(www.hynix.com) to check the high temperature self-refresh
rate availability.
EMRS(3) Programming: Reserved
*1 : EMRS(3) is reserved for future use and all bits except BA0 and BA1 must be programmed to 0 when setting
the mode register during initialization.
BA
0*
1
2
BA
BA1
0
0
1
1
1
1
BA
0
BA
0*
0
1
2
BA0
A
0
1
0
1
BA
15 ~
1
1
A
BA
13
1
EMRS(3):Reserved
0
A
A
15 ~
12
MRS mode
EMRS(1)
EMRS(2)
A
13
A
MRS
11
0*
A
1
12
A
10
A
11
*
1
A
9
A
10
A
8
1
0
A
A7
9
SRF
A
7
A
0*
8
Hign Temp Self-refresh
1
A
6
A
7
Rate Enable
A
Disable
Enable
5
A
6
0*
A
4
1
A
5
A
3
A
4
A
2
A
1HY5PS12421(L)M
3
HY5PS12821(L)M
A
1
A
2
A
0
A
1
Address Field
Extended Mode
Register(2)
A
0
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