hy5ps1g821m Hynix Semiconductor, hy5ps1g821m Datasheet - Page 5

• Manufacturer Part Number: hy5ps1g821m
• Description: 1gb Ddr2 Sdram
• Manufacturer: Hynix Semiconductor

Rev. 0.2 / Oct. 2005
1. Description
Ordering Information
Note: -X* is the speed bin, refer to the Operation
Frequency table for complete Part No.
HY5PS1G421(L)M-X*
HY5PS1G821(L)M-X*
1.1 Device Features & Ordering Information
1.1.1 Key Features
• Dual Die Package( 512Mb DDR2 * 2)
• VDD, VDDQ=1.8V +/- 0.1V
• All inputs and outputs are compatible with SSTL_18 interface
• Fully differential clock inputs (CK, /CK) operation
• Double data rate interface
• Source synchronous-data transaction aligned to bidirectional data strobe (DQS, DQS)
• Differential Data Strobe (DQS, DQS)
• Data outputs on DQS, DQS edges when read (edged DQ)
• Data inputs on DQS centers when write(centered DQ)
• On chip DLL align DQ, DQS and DQS transition with CK transition
• DM mask write data-in at the both rising and falling edges of the data strobe
• All addresses and control inputs except data, data strobes and data masks latched on the rising
• Programmable CAS latency 3, 4, 5 supported
• Programmable additive latency 0, 1, 2, 3, 4 supported
• Programmable burst length 4/8 with both nibble sequential and interleave mode
• Internal 4bank operations with single pulsed RAS
• Auto refresh and self refresh supported
• tRAS lockout supported
• 8K refresh cycles /64ms
• JEDEC standard 60ball FBGA(x4/x8)
• Full strength driver option controlled by EMRS
• On Die Termination supported
• Off Chip Driver Impedance Adjustment supported
• Read Data Strobe supported (x8 only)
• Self-Refresh High Temperature Entry
Part No.
edges of the clock
Configuration Package
256Mx4
128Mx8
63Ball
Operating Frequency
Grade
-C4
-E3
tCK(ns)
3.75
5
CL
3
4
1HY5PS12421(L)M
HY5PS12821(L)M
tRCD
3
4
tRP
3
4
Unit
Clk
Clk
5