hy5ps1g821m Hynix Semiconductor, hy5ps1g821m Datasheet - Page 36

• Manufacturer Part Number: hy5ps1g821m
• Description: 1gb Ddr2 Sdram
• Manufacturer: Hynix Semiconductor

Rev. 0.2 / Oct. 2005
Writes interrupted by a write
Burst write can only be interrupted by another write with 4 bit burst boundary. Any other case of write inter-
rupt is not allowed.
Write Burst Interrupt Timing Example: (CL=3, AL=0, RL=3, WL=2, BL=8)
Notes:
1. Write burst interrupt function is only allowed on burst of 8. Burst interrupt of 4 is prohibited.
2. Write burst of 8 can only be interrupted by another Write command. Write burst interruption by Read
3. Write burst interrupt must occur exactly two clocks after previous Write command. Any other Write
4. Write burst interruption is allowed to any bank inside DRAM.
5. Write burst with Auto Precharge enabled is not allowed to interrupt.
6. Write burst interruption is allowed by another Write with Auto Precharge command.
7. All command timings are referenced to burst length set in the mode register. They are not referenced
CK/CK
DQS/DQS
CMD
DQs
command or Precharge command is prohibited.
burst interrupt timings are prohibited.
to actual burst. For example, minimum Write to Precharge timing is WL+BL/2+tWR where tWR starts
with the rising clock after the un-interrupted burst end and not from the end of actual burst end.
NOP
Write A
NOP
Write B
A0
A1
NOP
A2
A3
NOP
B0
B1
NOP
B2
B3
NOP
B4
1HY5PS12421(L)M
HY5PS12821(L)M
B5
NOP
B6
B7
NOP
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