hy5ps1g821m Hynix Semiconductor, hy5ps1g821m Datasheet - Page 3

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hy5ps1g821m

Manufacturer Part Number
hy5ps1g821m
Description
1gb Ddr2 Sdram
Manufacturer
Hynix Semiconductor
Datasheet
Rev. 0.2 / Oct. 2005
Contents
1. Description
2. Functioanal Description
3. Truth Tables
4. Operating Conditions
1.1 Device Features and Ordering Information
1.2 Pin configuration
1.3 Pin Description
2.1 Simplified State Diagram
2.2 Functional Block Diagram
2.3 Basic Function & Operation of DDR2 SDRAM
2.4 Bank Activate Command
2.5 Read and Write Command
2.6 Precharge Operation
2.7 Auto Precharge Operation
2.8 Refresh Commands
2.9 Power Down
2.10 Asynchronous CKE Low Event
2.11 No Operation Command
2.12 Deselect Command
3.1 Command Truth Table
3.2 Clock Enable(CKE) Truth Table for Synchronous Transistors
3.3 Data Mask Truth Table
4.1 Absolute Maximum DC Ratings
4.2 Operating Temperature Condition
1.1.1 Key Feaures
1.1.2 Ordering Information
1.1.3 Ordering Frequency
1.2.1 256M x4 DDR2 DDP Pin Configuration
1.2.2 128M x8 DDR2 DDP Pin Configuration
2.2.1 Functional Block Diagram(256M x4)
2.2.2 Functional Block Diagram(128M x8)
2.3.1 Power up and Initialization
2.3.2 Programming the Mode and Extended Mode Registers
2.3.2.1 DDR2 SDRAM Mode Register Set(MRS)
2.3.2.2 DDR2 SDRAM Extended Mode Register Set
2.3.2.3 Off-Chip Driver(OCD) Impedance Adjustment
2.3.2.4 ODT(On Die Termination)
2.5.1 Posted CAS
2.5.2 Burst Mode Operation
2.5.3 Burst Read Command
2.5.4 Burst Write Operation
2.5.5 Write Data Mask
2.8.1 Auto Refresh Command
2.8.2 Self Refresh Command
1HY5PS12421(L)M
HY5PS12821(L)M
3

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