A25L05PMF-50 AMICC [AMIC Technology], A25L05PMF-50 Datasheet - Page 11

• Manufacturer Part Number: A25L05PMF-50
• Description: 8 Mbit, Low Voltage, Serial Flash Memory With 50 MHz SPI Bus Interface
• Manufacturer: AMICC [AMIC Technology]

Read Status Register (RDSR)
The Read Status Register (RDSR) instruction allows the Status
Register to be read. The Status Register may be read at any
time, even while a Program, Erase or Write Status Register
cycle is in progress. When one of these cycles is in progress, it
is recommended to check the Write In Progress (WIP) bit
before sending a new instruction to the device. It is also
possible to read the Status Register continuously, as shown in
Figure 6.
Table 4. Status Register Format
The status and control bits of the Status Register are as
follows:
WIP bit. The Write In Progress (WIP) bit indicates whether the
memory is busy with a Write Status Register, Program or Erase
cycle. When set to 1, such a cycle is in progress, when reset to
Figure 6. Read Status Register (RDSR) Instruction Sequence and Data-Out Sequence
PRELIMINARY
Status Register
SRWD
Write Protect
b7
0
C
D
Q
S
(May 2005, Version 0.0)
0
Block Protect Bits
BP2
0 1
High Impedance
Write Enable Latch Bit
BP1
2 3 4
Instruction
Write In Progress Bit
BP0 WEL WIP
5 6
7
MSB
7
b0
8
Status Register Out
6
9
5
10
4
11 12 13 14 15
10
3
0 no such cycle is in progress.
WEL bit. The Write Enable Latch (WEL) bit indicates the status
of the internal Write Enable Latch. When set to 1 the internal
Write Enable Latch is set, when set to 0 the internal Write
Enable Latch is reset and no Write Status Register, Program or
Erase instruction is accepted.
BP2, BP1, BP0 bits. The Block Protect (BP2, BP1, BP0) bits
are non-volatile. They define the size of the area to be software
protected against Program and Erase instructions. These bits
are written with the Write Status Register (WRSR) instruction.
When one or both of the Block Protect (BP2, BP1, BP0) bits is
set to 1, the relevant memory area (as defined in Table 1.)
becomes protected against Page Program (PP) and Sector
Erase (SE) instructions. The Block Protect (BP2, BP1, BP0)
bits can be written provided that the Hardware Protected mode
has not been set. The Bulk Erase (BE) instruction is executed if,
and only if, both Block Protect (BP2, BP1, BP0) bits are 0.
SRWD bit. The Status Register Write Disable (SRWD) bit is
operated in conjunction with the Write Protect (
Status Register Write Disable (SRWD) bit and Write Protect
(
Protected mode (when the Status Register Write Disable
(SRWD) bit is set to 1, and Write Protect (
In this mode, the non-volatile bits of the Status Register
(SRWD, BP2, BP1, BP0) become read-only bits and the Write
Status Register (WRSR) instruction is no longer accepted for
execution.
W
2
) signal allow the device to be put in the Hardware
1
0
MSB
7
Status Register Out
6
5
4
3
AMIC Technology Corp.
2
1
0
7
W
) is driven Low).
A25L80P
W
) signal. The