A25L05PMF-50 AMICC [AMIC Technology], A25L05PMF-50 Datasheet - Page 18

• Manufacturer Part Number: A25L05PMF-50
• Description: 8 Mbit, Low Voltage, Serial Flash Memory With 50 MHz SPI Bus Interface
• Manufacturer: AMICC [AMIC Technology]

Bulk Erase (BE)
The Bulk Erase (BE) instruction sets all bits to 1 (FFh). Before
it can be accepted, a Write Enable (WREN) instruction must
previously have been executed. After the Write Enable (WREN)
instruction has been decoded, the device sets the Write Enable
Latch (WEL).
The Bulk Erase (BE) instruction is entered by driving Chip
Select (
Input (D). Chip Select (
duration of the sequence.
The instruction sequence is shown in Figure 12. Chip Select
(
code has been latched in, otherwise the Bulk Erase instruction
Figure 12. Bulk Erase (BE) Instruction Sequence
PRELIMINARY
S
) must be driven High after the eighth bit of the instruction
S
) Low, followed by the instruction code on Serial Data
(May 2005, Version 0.0)
S
) must be driven Low for the entire
Notes: Address bits A23 to A20 are Don’t Care.
C
D
S
0
1 2 3
Instruction
17
is not executed. As soon as Chip Select (
self-timed Bulk Erase cycle (whose duration is t
While the Bulk Erase cycle is in progress, the Status Register
may be read to check the value of the Write In Progress (WIP)
bit. The Write In Progress (WIP) bit is 1 during the self-timed
Bulk Erase cycle, and is 0 when it is completed. At some
unspecified time before the cycle is completed, the Write
Enable Latch (WEL) bit is reset.
The Bulk Erase (BE) instruction is executed only if all Block
Protect (BP2, BP1, BP0) bits are 0. The Bulk Erase (BE)
instruction is ignored if one, or more, sectors are protected.
4 5 6 7
AMIC Technology Corp.
S
) is driven High, the
A25L80P
BE
) is initiated.