A25L05PMF-50 AMICC [AMIC Technology], A25L05PMF-50 Datasheet - Page 23

• Manufacturer Part Number: A25L05PMF-50
• Description: 8 Mbit, Low Voltage, Serial Flash Memory With 50 MHz SPI Bus Interface
• Manufacturer: AMICC [AMIC Technology]

POWER-UP AND POWER-DOWN
At Power-up and Power-down, the device must not be selected
(that is Chip Select (
until V
­
­
Usually a simple pull-up resistor on Chip Select (
used to insure safe and proper Power-up and Power-down.
To avoid data corruption and inadvertent write operations
during power up, a Power On Reset (POR) circuit is included.
The logic inside the device is held reset while V
the POR threshold value, V
the device does not respond to any instruction.
Moreover, the device ignores all Write Enable (WREN), Page
Program (PP), Sector Erase (SE), Bulk Erase (BE) and Write
Status Register (WRSR) instructions until a time delay of t
has elapsed after the moment that V
threshold. However, the correct operation of the device is not
guaranteed if, by this time, V
Status Register, Program or Erase instructions should be sent
until the later of:
Figure 17-1. Power-up Timing
PRELIMINARY
V
V
CC
SS
CC
(min) at Power-up, and then for a further delay of t
at Power-down
reaches the correct value:
(May 2005, Version 0.0)
S
) must follow the voltage applied on V
V
V
WI
CC
CC
CC
– all operations are disabled, and
(min)
(max)
is still below V
V
CC
CC
rises above the VWI
CC
(min). No Write
CC
is less than
S
) can be
VSL
PUW
CC
)
t
22
PU
­
- t
These values are specified in Table 6.
If the delay, t
V
even if the t
At Power-up, the device is in the following state:
­
­
Normal precautions must be taken for supply rail decoupling, to
stabilize the V
V
pins. (Generally, this capacitor is of the order of 0.1µF).
At Power-down, when V
below the POR threshold value, V
and the device does not respond to any instruction. (The
designer needs to be aware that if a Power-down occurs while
a Write, Program or Erase cycle is in progress, some data
corruption can result.)
CC
CC
t
The device is in the Standby mode (not the Deep
Power-down mode).
The Write Enable Latch (WEL) bit is reset.
VSL
(min), the device can be selected for READ instructions
PUW
rail decoupled by a suitable capacitor close to the package
afterV
after V
Full Device Access
PUW
CC
CC
CC
VS L
delay is not yet fully elapsed.
passed the V
feed. Each device in a system should have the
passed the VWI threshold
, has elapsed, after V
CC
drops from the operating voltage, to
AMIC Technology Corp.
CC
(min) level
time
WI
, all operations are disabled
CC
has risen above
A25L80P