A25L05PMF-50 AMICC [AMIC Technology], A25L05PMF-50 Datasheet - Page 17

• Manufacturer Part Number: A25L05PMF-50
• Description: 8 Mbit, Low Voltage, Serial Flash Memory With 50 MHz SPI Bus Interface
• Manufacturer: AMICC [AMIC Technology]

Sector Erase (SE)
The Sector Erase (SE) instruction sets all bits to 1 (FFh).
Before it can be accepted, a Write Enable (WREN) instruction
must previously have been executed. After the Write Enable
(WREN) instruction has been decoded, the device sets the
Write Enable Latch (WEL).
The Sector Erase (SE) instruction is entered by driving Chip
Select (
Input (D). Chip Select (
duration of the sequence.
The instruction sequence is shown in Figure 11. Chip Select
(
code has been latched in, otherwise the Sector Erase
Figure 11. Sector Erase (SE) Instruction Sequence
PRELIMINARY
S
) must be driven High after the eighth bit of the instruction
S
) Low, followed by the instruction code on Serial Data
(May 2005, Version 0.0)
S
) must be driven Low for the entire
C
D
S
Notes: Address bits A23 to A20 are Don’t Care.
0 1
2 3 4
Instruction
5 6
16
7
MSB
23
23
instruction is not executed. As soon as Chip Select (
driven High, the self-timed Sector Erase cycle (whose duration
is t
the Status Register may be read to check the value of the Write
In Progress (WIP) bit. The Write In Progress (WIP) bit is 1
during the self-timed Sector Erase cycle, and is 0 when it is
completed. At some unspecified time before the cycle is
completed, the Write Enable Latch (WEL) bit is reset.
The Sector Erase (SE) instruction is executed only if all
Block Protect (BP2, BP1, BP0) bits are 0. The Sector Erase
(SE) instruction is ignored if one, or more, sectors are
protected.
8
22 21
BE
9
) is initiated. While the Sector Erase cycle is in progress,
24-Bit Address
10
3 2 1
28 29 30 31
0 0
AMIC Technology Corp.
A25L80P
S
) is