A25L05PMF-50 AMICC [AMIC Technology], A25L05PMF-50 Datasheet - Page 14

• Manufacturer Part Number: A25L05PMF-50
• Description: 8 Mbit, Low Voltage, Serial Flash Memory With 50 MHz SPI Bus Interface
• Manufacturer: AMICC [AMIC Technology]

Read Data Bytes (READ)
The device is first selected by driving Chip Select (
instruction code for the Read Data Bytes (READ) instruction is
followed by a 3-byte address (A23-A0), each bit being
latched-in during the rising edge of Serial Clock (C). Then the
memory contents, at that address, is shifted out on Serial Data
Output (Q), each bit being shifted out, at a maximum frequency
f
The instruction sequence is shown in Figure 8. The first byte
addressed can be at any location. The address is automatically
incremented to the next higher address after each byte of data
is shifted out. The whole memory can, therefore, be read with a
Figure 8. Read Data Bytes (READ) Instruction Sequence and Data-Out Sequence
PRELIMINARY
R
, during the falling edge of Serial Clock (C).
S
C
D
Q
(May 2005, Version 0.0)
0 1
High Impedance
2 3 4
Instruction
5 6
7
MSB
23 22 21
S
8
) Low. The
9
24-Bit Address
10
13
3 2 1
28 29 30 31 32 33 34 35 36 37 38 39
single Read Data Bytes (READ) instruction. When the highest
address is reached, the address counter rolls over to 000000h,
allowing the read sequence to be continued indefinitely.
The Read Data Bytes (READ) instruction is terminated by
driving Chip Select (
High at any time during data output. Any Read Data Bytes
(READ) instruction, while an Erase, Program or Write cycle is
in progress, is rejected without having any effects on the cycle
that is in progress.
0
MSB
7
6 5 4 3 2 1 0
Data Out 1
S
) High. Chip Select (
AMIC Technology Corp.
7
Data Out 2
S
A25L80P
) can be driven