A25L05PMF-50 AMICC [AMIC Technology], A25L05PMF-50 Datasheet - Page 9

• Manufacturer Part Number: A25L05PMF-50
• Description: 8 Mbit, Low Voltage, Serial Flash Memory With 50 MHz SPI Bus Interface
• Manufacturer: AMICC [AMIC Technology]

INSTRUCTIONS
All instructions, addresses and data are shifted in and out of
the device, most significant bit first.
Serial Data Input (D) is sampled on the first rising edge of
Serial Clock (C) after Chip Select (
one-byte instruction code must be shifted in to the device, most
significant bit first, on Serial Data Input (D), each bit being
latched on the rising edges of Serial Clock (C).
The instruction set is listed in Table 3.
Every instruction sequence starts with a one-byte instruction
code. Depending on the instruction, this might be followed by
address bytes, or by data bytes, or by both or none.
In the case of a Read Data Bytes (READ), Read Data Bytes at
Higher Speed (Fast_Read), Read Status Register (RDSR) or
Release from Deep Power-down, Read Device Identification
and Read Electronic Signature (RES) instruction, the shifted-in
instruction sequence is followed by a data-out sequence. Chip
Select (
Table 3. Instruction Set
PRELIMINARY
FAST_READ
Instruction
WREN
WRSR
RDSR
READ
WRDI
RDID
RES
DP
PP
SE
BE
S
) can be driven High after any bit of the data-out
Write Enable
Write Disable
Read Status Register
Write Status Register
Read Data Bytes
Read Data Bytes at Higher Speed
Page Program
Sector Erase
Bulk Erase
Deep Power-down
Read Device Identification
Release from Deep Power-down,
and Read Electronic Signature
Release from Deep Power-down
(May 2005, Version 0.0)
Description
S
) is driven Low. Then, the
One-byte Instruction Code
0000 0110
0000 0100
0000 0101
0000 0001
0000 0011
0000 0010
1101 1000
1100 0111
1011 1001
0000 1011
1001 1111
1010 1011
8
sequence is being shifted out.
In the case of a Page Program (PP), Sector Erase (SE), Bulk
Erase (BE), Write Status Register (WRSR), Write Enable
(WREN), Write Disable (WRDI) or Deep Power-down (DP)
instruction, Chip Select (
byte boundary, otherwise the instruction is rejected, and is not
executed. That is, Chip Select (
number of clock pulses after Chip Select (
is an exact multiple of eight.
All attempts to access the memory array during a Write Status
Register cycle, Program cycle or Erase cycle are ignored, and
the internal Write Status Register cycle, Program cycle or
Erase cycle continues unaffected.
D8h
C7h
ABh
01h
0Bh
B9h
9Fh
06h
04h
05h
03h
02h
Address
Bytes
0
0
0
0
3
3
3
3
0
0
0
0
0
S
) must be driven High exactly at a
AMIC Technology Corp.
S
) must driven High when the
Dummy
Bytes
0
0
0
0
0
1
0
0
0
0
0
3
0
S
) being driven Low
A25L80P
Data Bytes
1 to 256
1 to ∞
1 to ∞
1 to ∞
1 to ∞
1 to 3
0
0
1
0
0
0
0