CS42428 CIRRUS [Cirrus Logic], CS42428 Datasheet - Page 15

• Manufacturer Part Number: CS42428
• Description: 114 dB, 192kHz 8-Ch CODEC WITH PLL
• Manufacturer: CIRRUS [Cirrus Logic]

sample rate applications are shown in Table 1. The lock time is the worst case for an Fs transition from un-
locked state to locking to 192 kHz.
It is important to treat the LPFLT pin as a low level analog input. It is suggested that the ground end of the
PLL filter be returned directly to the AGND pin independently of the digital ground plane.
3.4.2
A special clock switching mode is available that allows the clock that is input through the OMCK pin to
be used as the internal master clock. This feature is controlled by the SW_CTRLx bits in register “Clock
Control (address 06h)” on page 37. An advanced auto switching mode is also implemented to maintain
master clock functionality. The clock auto switching mode allows the clock input through OMCK to be
used as a clock in the system without any disruption when the PLL loses lock, for example, when the
LRCK is removed from ADC_LRCK. This clock switching is done glitch free.
3.4.3
In master mode, the serial interface timings are derived from an external clock attached to OMCK or the
output of the PLL with an input reference to the ADC_LRCK input from the ADC serial port. The DAC
Serial Port and ADC Serial Port can both be masters only when OMCK is used as the clock source. When
using the PLL output, the ADC Serial Port must be slave and the DAC Serial Port can operate in Master
Mode. Master clock selection and operation is configured with the SW_CTRL1:0 and CLK_SEL bits in
the Clock Control Register (See “Clock Control (address 06h)” on page 37).
The sample rate to OMCK ratios and OMCK frequency requirements for Master mode operation are
shown in Table 2.
3.4.4
In Slave mode, DAC_LRCK, DAC_SCLK and/or ADC_LRCK and ADC_SCLK operate as inputs. The
Left/Right clock signal must be equal to the sample rate, Fs and must be synchronously derived from the
supplied master clock, OMCK or must be synchronous to the supplied ADC_LRCK used as the input to
OMCK System Clock Mode
Master Mode
Slave Mode
Sample
(kHz)
Rate
192
48
96
Fs Range (kHz) RFILT (kΩ) CFILT (pF) CRIP (pF) Settling time
12.2880 18.4320 24.5760
256x
32 to 192
-
-
Single Speed
(4 to 50 kHz)
384x
-
-
Table 1. PLL External Component Values
Table 2. Common OMCK Clock Frequencies
512x
10
-
-
12.2880 18.4320 24.5760
128x
-
-
2700
(50 to 100 kHz)
Double Speed
OMCK (MHz)
192x
-
-
680
256x
-
-
12.2880 18.4320 24.5760
64x
11 ms
-
-
(100 to 192 kHz)
Quad Speed
96x
-
-
128x
-
-
CS42428
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