CS42428 CIRRUS [Cirrus Logic], CS42428 Datasheet - Page 39

• Manufacturer Part Number: CS42428
• Description: 114 dB, 192kHz 8-Ch CODEC WITH PLL
• Manufacturer: CIRRUS [Cirrus Logic]

5.8
5.8.1
5.9
5.9.1
5.9.2
RATIO7(2
Reserved
7
7
OMCK/PLL_CLK Ratio (address 07h) (Read Only)
OMCK/PLL_CLK RATIO (RATIOX)
Clock Status (address 08h) (Read Only)
SYSTEM CLOCK SELECTION (ACTIVE_CLK)
PLL CLOCK FREQUENCY (PLL_CLKX)
1
Default = sixth
Function:
Default = x
0 - Output of PLL
1 - OMCK
Function:
Default = xxxh
Function:
)
This register allows the user to find the exact absolute frequency of the recovered MCLK coming from
the PLL. This value is represented as an integer (RATIO7:6) and a fractional (RATIO5:0) part. For
example, an OMCK/PLL_CLK ratio of 1.5 would be displayed as 60h.
This bit identifies the source of the internal system clock (MCLK).
The CS42428 will auto-detect the ratio between the OMCK and the recovered clock from the PLL,
which is displayed in register 07h. Based on this ratio, the absolute frequency of the PLL clock can
be determined, and this information is displayed according to the following table. If the absolute fre-
quency of the PLL clock does not match one of the given frequencies, this register will display the
closest available value.
NOTE: These bits are set to ‘111’b when the FRC_PLL_LK bit is ‘1’b.
RATIO6(2
Reserved
6
6
PLL_CLK2
0
)
0
0
0
0
1
1
1
1
RATIO5(2
Reserved
5
5
Table 13. PLL Clock Frequency Detection
PLL_CLK1
-1
)
0
0
1
1
0
0
1
1
RATIO4(2
Reserved
4
4
-2
PLL_CLK0
)
0
1
0
1
0
1
0
1
RATIO3(2
Active_CLK
3
3
-3
)
16.3840 MHz
22.5792 MHz
24.5760 MHz
45.1584 MHz
49.1520 MHz
11.2896 MHz
Description
8.1920 MHz
12.288 MHz
RATIO2(2
PLL_CLK2
2
2
-4
)
RATIO1(2
PLL_CLK1
1
1
-5
)
CS42428
RATIO0(2
PLL_CLK0
0
0
-6
)
39