CS42428 CIRRUS [Cirrus Logic], CS42428 Datasheet - Page 38

• Manufacturer Part Number: CS42428
• Description: 114 dB, 192kHz 8-Ch CODEC WITH PLL
• Manufacturer: CIRRUS [Cirrus Logic]

5.7.2
5.7.3
5.7.4
5.7.5
38
OMCK FREQUENCY (OMCK FREQX)
PLL LOCK TO LRCK (PLL_LRCK)
MASTER CLOCK SOURCE SELECT (SW_CTRLX)
FORCE PLL LOCK (FRC_PLL_LK)
Default = 00
Function:
Default = 0
0 - Disabled
1 - Enabled
Function:
Default = 01
Function:
Default = 0
Function:
SW_CTRL1 SW_CTRL0
When enabled, the internal PLL of the CS42428 will lock to the LRCK of the ADC serial port
(ADC_LRCK) while the ADC_SP is in slave mode.
Sets the appropriate frequency for the supplied OMCK.
These two bits, along with the UNLOCK bit in register “Interrupt Status (address 20h) (Read Only)”
on page 46, determine the master clock source for the CS42428. When SW_CTRL1 and SW_CTRL0
are set to '00'b, selecting the output of the PLL as the internal clock source, and the PLL becomes
unlocked, then RMCK will equal OMCK, but all internal and serial port timings are not valid.
This bit is used to enable the PLL to lock to the ADC_LRCK with the absence of a clock signal on
OMCK. When set to a ‘1’b, the auto-detect sample frequency feature will be disabled. The OM-
CK/PLL_CLK Ratio (address 07h) (Read Only) register contents are not valid and the PLL_CLK[2:0]
bits will be set to ‘111’b. Use the DE-EMPH[1:0] bits to properly apply de-emphasis filtering.
OMCK Freq1 OMCK Freq0 Description
0
0
1
1
0
0
1
1
0
1
0
1
Table 11. OMCK Frequency Settings
0
1
0
1
Table 12. Master Clock Source Select
UNLOCK
X
X
0
1
0
1
11.2896 MHz or 12.2880 MHz
16.9344 MHz or 18.4320 MHz
22.5792 MHz or 24.5760 MHz
Reserved
Manual setting, MCLK sourced from
Manual setting, MCLK sourced from OMCK.
Hold, keep same MCLK source.
Auto switch, MCLK sourced from OMCK.
Auto switch, MCLK sourced from PLL.
Auto switch, MCLK sourced from OMCK.
Description
PLL.
CS42428