CS42428 CIRRUS [Cirrus Logic], CS42428 Datasheet - Page 37

• Manufacturer Part Number: CS42428
• Description: 114 dB, 192kHz 8-Ch CODEC WITH PLL
• Manufacturer: CIRRUS [Cirrus Logic]

5.6.6
5.6.7
5.7
5.7.1
RMCK_DIV1
7
DAC SERIAL PORT MASTER/SLAVE SELECT (DAC_SP M/S)
ADC SERIAL PORT MASTER/SLAVE SELECT (ADC_SP M/S)
Clock Control (address 06h)
RMCK DIVIDE (RMCK_DIVX)
Default = 1
Function:
Default = 1
Function:
Default = 00
Function:
In Master mode, DAC_SCLK and DAC_LRCK are outputs. Internal dividers will divide the master
clock to generate the serial clock and left/right clock. In Slave mode, DAC_SCLK and DAC_LRCK
become inputs.
In Master mode, ADC_SCLK and ADC_LRCK are outputs. Internal dividers will divide the master
clock to generate the serial clock and left/right clock. In Slave mode, ADC_SCLK and ADC_LRCK
become inputs.
To use the PLL to lock to ADC_LRCK, the ADC_SP must be in slave mode. When using the PLL to
lock to LRCK, if ADC_SDOUT is configured to be clocked by the ADC_SP, then both ADC_SCLK and
ADC_LRCK must be present. If ADC_SDOUT is configured to be clocked by the DAC_SP, then only
the ADC_LRCK signal must be applied.
Divides/multiplies the internal MCLK, either from the PLL or OMCK, by the selected factor.
RMCK_DIV0
6
RMCK_DIV1 RMCK_DIV0
OMCK Freq1
5
0
0
1
1
Table 10. RMCK Divider Settings
OMCK Freq0
4
0
1
0
1
PLL_LRCK
Description
Multiply by 2
Divide by 1
Divide by 2
Divide by 4
3
SW_CTRL1
2
SW_CTRL0
1
CS42428
FRC_PLL_LK
0
37