CS42428 CIRRUS [Cirrus Logic], CS42428 Datasheet - Page 27

• Manufacturer Part Number: CS42428
• Description: 114 dB, 192kHz 8-Ch CODEC WITH PLL
• Manufacturer: CIRRUS [Cirrus Logic]

not, as desired. To begin a read, bring CS low, send out the chip address and set the read/write bit (R/W)
high. The next falling edge of CCLK will clock out the MSB of the addressed register (CDOUT will leave
the high impedance state). If the MAP auto increment bit is set to 1, the data for successive registers will
appear consecutively.
3.6.2
In I
There is no CS pin. Pins AD0 and AD1 form the two least significant bits of the chip address and should
be connected through a resistor to VLC or DGND as desired. The state of the pins is sensed while the
CS42428 is being reset.
The signal timings for a read and write cycle are shown in Figure 18 and Figure 19. A Start condition is
defined as a falling transition of SDA while the clock is high. A Stop condition is a rising transition while
the clock is high. All other transitions of SDA occur while the clock is low. The first byte sent to the
CS42428 after a Start condition consists of a 7 bit chip address field and a R/W bit (high for a read, low
for a write). The upper 5 bits of the 7-bit address field are fixed at 10011. To communicate with a CS42428,
the chip address field, which is the first byte sent to the CS42428, should match 10011 followed by the
settings of the AD1 and AD0. The eighth bit of the address is the R/W bit. If the operation is a write, the
next byte is the Memory Address Pointer (MAP) which selects the register to be read or written. If the op-
eration is a read, the contents of the register pointed to by the MAP will be output. Setting the auto incre-
ment bit in MAP allows successive reads or writes of consecutive registers. Each byte is separated by an
acknowledge bit. The ACK bit is output from the CS42428 after each input byte is read, and is input to the
CS42428 from the microcontroller after each transmitted byte.
2
C mode, SDA is a bidirectional data line. Data is clocked into and out of the part by the clock, SCL.
SCL
SDA
SDA
SCL
I
2
C Mode
START
START
0
1
CHIP ADDRESS (WRITE)
0
1
1
CHIP ADDRESS (WRITE)
0
1
0
2
0
1
0
3
2
1 AD1 AD0 0
1
4
3
1 AD1 AD0 0
5
4
Figure 19. Control Port Timing, I
Figure 18. Control Port Timing, I
6
5
7
6
ACK
8
7
9
INCR
ACK
8
10 11
6
INCR
9
5
MAP BYTE
10 11
12 13 14 15
6
4
MAP BYTE
5
3
12
4
2
13 14 15
1
3
16
0
2
ACK
STOP
17 18
1
START
16 17 18
0
ACK
19
1
2
2
20 21 22 23 24
CHIP ADDRESS (READ)
0
7
C Slave Mode Read
C Slave Mode Write
0
19
6
DATA
1
1 AD1 AD0 1
24 25
1
0
ACK
25
26
26 27 28
27 28
7
ACK
DATA +1
6
7
DATA
1
0
ACK
0
DATA +1
7
7
DATA +n
6
0
1
DATA + n
7
0
CS42428
ACK
0
STOP
ACK
NO
STOP
27