CS42428 CIRRUS [Cirrus Logic], CS42428 Datasheet - Page 61

• Manufacturer Part Number: CS42428
• Description: 114 dB, 192kHz 8-Ch CODEC WITH PLL
• Manufacturer: CIRRUS [Cirrus Logic]

SWITCHING CHARACTERISTICS
VA = 5 V, VD =VLC= 3.3 V, VLS = 1.8 V to 5.25 V; Inputs: Logic 0 = DGND, Logic 1 = VLS, C
Notes: 13. After powering up the CS42428, RST should be held low after the power supplies and clocks are settled.
RST pin Low Pulse Width
PLL Clock Recovery Sample Rate Range
RMCK output jitter
RMCK output duty cycle
OMCK Duty Cycle
DAC_SCLK, ADC_SCLK Duty Cycle
DAC_LRCK, ADC_LRCK Duty Cycle
Master Mode
RMCK to DAC_SCLK, ADC_SCLK active edge delay
RMCK to DAC_LRCK, ADC_LRCK delay
Slave Mode
DAC_SCLK, ADC_SCLK Falling Edge to
ADC_SDOUT, ADC_SDOUT Output Valid
DAC_LRCK, ADC_LRCK Edge to MSB Valid
DAC_SDIN Setup Time Before DAC_SCLK Rising
Edge
DAC_SDIN Hold Time After DAC_SCLK Rising Edge
DAC_SCLK, ADC_SCLK High Time
DAC_SCLK, ADC_SCLK Low Time
DAC_SCLK, ADC_SCLK rising to DAC_LRCK,
SAI_LRCK Edge
DAC_LRCK, ADC_LRCK Edge to DAC_SCLK,
ADC_SCLK Rising
Figure 56. Serial Audio Port Master Mode Timing
DAC_SCLK
ADC_SCLK
DAC_LRCK
ADC_LRCK
(output)
(output)
14. See Table 2 on page 15 for suggested OMCK frequencies
15. Limit the loading on RMCK to 1 CMOS load if operating above 24.576 MHz.
RM CK
Parameters
t
smd
t
lmd
(Note 13)
(Note 15)
(Note 14)
(For CQ, T
Symbol
t
t
t
t
t
t
t
t
sckh
lrckd
lrcks
smd
dpd
lrpd
t
t
sckl
lmd
dh
ds
A
A DC_SDOUT
DAC_S DINx
DA C_LRCK
ADC_LRCK
DA C_SCLK
ADC_SCLK
Figure 57. Serial Audio Port Slave Mode Timing
= -10 to +70° C; For DQ, T
(input)
(input)
Min
30
45
40
45
45
20
20
25
25
1
0
0
-
t
lrckd
t
lrpd
t
lrcks
Typ
200
50
50
50
50
t
-
-
-
-
-
-
-
-
-
-
-
-
ds
A
M S B
t
sckh
t
dh
= -40 to +85° C;
L
= 30 pF)
Max
200
55
60
55
55
10
10
50
20
10
30
-
-
-
-
-
-
t
sckl
CS42428
t dpd
MS B-1
ps RMS
Units
kHz
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
%
%
%
%
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