MC68306 Motorola, MC68306 Datasheet - Page 101

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MC68306

Manufacturer Part Number
MC68306
Description
Integrated EC000 Processor
Manufacturer
Motorola
Datasheet

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x = Address bit is a don’t care, CSA bit must be 0 to allow match.
• = Address bit must match CSA bit for chip select to occur.
CSDT3–0—Chip Select DTACK Wait State Selection
MOTOROLA
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Table 5-2 shows the entire range of address bits that must match for a chip select to
occur.
This field determines whether automatic DTACK is returned, and how many wait states
are inserted if automatic DTACK is enabled. When automatic DTACK is selected, the
write portion of a TAS indivisible cycle is the same length as a normal write cycle to the
same location. Any external DTACK generation circuit must recognize that AS remains
asserted throughout a read-write indivisible cycle, if it supports TAS.
0000 = Automatic DTACK, 0 wait states
0001 = Automatic DTACK, 1 wait state
0010 = Automatic DTACK, 2 wait states
0011 = Automatic DTACK, 3 wait states
0100 = Automatic DTACK, 4 wait states
0101 = Automatic DTACK, 5 wait states
0110 = Automatic DTACK, 6 wait states
0111 = Automatic DTACK, 7 wait states
.........
1111 = A31–A17 must match CSA31–CSA17 in chip select address match
A31
x
A30
x
x
A29
x
x
x
A28
x
x
x
x
Table 5-2. Chip Select Match Bits
A27
x
x
x
x
x
MC68306 USER'S MANUAL
A26
x
x
x
x
x
x
A25
x
x
x
x
x
x
x
A24
1000 = Automatic DTACK, 8 wait states
1001 = Automatic DTACK, 9 wait states
1010 = Automatic DTACK, 10 wait states
1011 = Automatic DTACK, 11 wait states
1100 = Automatic DTACK, 12 wait states
1101 = Automatic DTACK, 13 wait states
1110 = Automatic DTACK, 14 wait states
1111 = No automatic DTACK, external
x
x
x
x
x
x
x
x
A23
x
x
x
x
x
x
x
x
x
DTACK required
A22
x
x
x
x
x
x
x
x
x
x
A21
x
x
x
x
x
x
x
x
x
x
x
A20
x
x
x
x
x
x
x
x
x
x
x
x
A19
x
x
x
x
x
x
x
x
x
x
x
x
x
A18
x
x
x
x
x
x
x
x
x
x
x
x
x
x
A17
5- 11
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x

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