MC68306 Motorola, MC68306 Datasheet - Page 130

• Manufacturer Part Number: MC68306
• Description: Integrated EC000 Processor
• Manufacturer: Motorola

6.4.1.3 STATUS REGISTER (DUSR). The DUSR indicates the status of the characters in
the FIFO and the status of the channel transmitter and receiver.
RB—Received Break
6-22
1 = An all-zero character of the programmed length has been received without a stop
0 = No break has been received.
bit. The RB bit is only valid when the RxRDY bit is set. Only a single FIFO
position is occupied when a break is received. Further entries to the FIFO are
inhibited until the channel RxDx returns to the high state for at least one-half bit
time, which is equal to two successive edges of the internal or external 1 clock
or 16 successive edges of the external 16 clock.
The received break circuit detects breaks that originate in the middle of a
received character. However, if a break begins in the middle of a character, it
must persist until the end of the next detected character time.
SB3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
DUSRA, DUSRB
Read Only
RESET:
RB
7
0
SB2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
FE
Table 6-4. SBx Control Bits
6
0
MC68306 USER'S MANUAL
SB1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
PE
5
0
SB0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
OE
4
0
TxEMP
Length 6-8 Bits
3
0
0.563
0.625
0.688
0.750
0.813
0.875
0.938
1.000
1.563
1.625
1.688
1.750
1.813
1.875
1.938
2.000
TxRDY
2
0
FFULL
1
0
RxRDY
Length 5 Bits
0
0
1.063
1.125
1.188
1.250
1.313
1.375
1.438
1.500
1.563
1.625
1.688
1.750
1.813
1.875
1.938
2.000
MOTOROLA