MC68306 Motorola, MC68306 Datasheet - Page 105

• Manufacturer Part Number: MC68306
• Description: Integrated EC000 Processor
• Manufacturer: Motorola

5.2.7.3 DRAM BANK CONFIGURATION REGISTER (LOW HALF)
FFFFFFE6/7 (DR1), FFFFFFE2/3 (DR0)
DRR—DRAM Read
DRFC6, 5, 2, 1—DRAM Bank Function Code 6, 5, 2, 1 Enable
DRM3–0—DRAM Bank Address Match
MOTOROLA
RESE
DRR
15
T:
U
This bit determines whether read cycles are permitted to DRAM bank space. If read and
write cycles are both inhibited, DRAM bank is inhibited.
This bit determines which function code accesses are permitted to DRAM bank space. If
all function code cycles are inhibited, the DRAM bank is inhibited.
This field determines which DRAM bank address bits must match address bits for
DRAM bank to occur. DRA bits not included in match must be set to zero, or else
DRAM bank is inhibited.
Table 5-4 shows the entire range of address bits that must match for a DRAM bank to
occur.
0 = Read cycles are inhibited to DRAM bank space
1 = Read cycles are permitted to DRAM bank space
0 = Function code n cycles are inhibited to DRAM bank space
1 = Function code n cycles are permitted to DRAM bank space
0000 = A31–A17 ignored in DRAM bank address match
0001 = A31 must match DRA31; A30–A17 ignored in DRAM bank address match
0010 = A31–A30 must match DRA31–DRA30; A29–A17 ignored in DRAM bank
.....
1111 = A31–A17 must match DRA31–DRA17 in DRAM bank address match
DRFC
14
6
U
DRFC
13
5
U
address match
12
—
U
11
—
U
DRFC
10
2
U
MC68306 USER'S MANUAL
DRFC
9
1
U
—
8
U
DRM3
7
U
DRM2
U
6
DRM1
5
U
DRM0
4
U
DRSZ2
3
U
DRSZ1
2
U
SUPERVISOR ONLY
DRSZ
U
1
0
DRDT
5- 15
U
0