MC68306 Motorola, MC68306 Datasheet - Page 42

• Manufacturer Part Number: MC68306
• Description: Integrated EC000 Processor
• Manufacturer: Motorola

STATE 12
STATE 13
STATE 14
STATE 15
STATE 16
STATE 17
STATE 18
STATE 19
STATE 5
STATE 6
STATE 7
STATE 5
STATE 6
STATE 7
STATE 8
STATE 9
3-10
FC2–FC0, the address bus lines, AS, and R/W remain unaltered.
data to be written are placed on the bus.
waits for D T A C K or BERR . If neither termination signal is asserted
before the falling edge at the close of S16, the processor inserts wait states
(full clock cycles) until either DTACK or BERR is asserted.
Case W1: DTACK with or without BERR .
UDS /LDS . As the clock rises at the end of S19, the processor
places the data bus in the high-impedance state, and drives
R/W high. The device negates DTACK or BERR at this time.
Case R2: DTACK and BERR on read.
AS and U D S /LDS are negated. The cycle terminates without the write
portion.
Case R3: BERR only on read.
AS and U D S /LDS are negated. The cycle terminates without the write
portion.
Case W2: BERR only on write.
The write portion of the cycle starts in S12. The valid function codes on
During S13, no bus signals are altered.
On the rising edge of S14, the processor drives R/W low.
During S15, the data bus is driven out of the high-impedance state as the
At the rising edge of S16, the processor asserts UDS /LDS . The processor
During S17, no bus signals are altered.
During S18, no bus signals are altered.
On the falling edge of the clock entering S19, the processor negates AS and
During S5, no bus signals are altered.
During S6, no bus signals are altered, and data from the device is ignored.
During S5, no bus signals are altered.
During S6, no bus signals are altered..
During S7, no bus signals are altered.
During S8, no bus signals are altered.
MC68306 USER'S MANUAL
MOTOROLA