MC68306 Motorola, MC68306 Datasheet - Page 50

• Manufacturer Part Number: MC68306
• Description: Integrated EC000 Processor
• Manufacturer: Motorola

When a bus request is made after the MPU has begun a bus cycle and before AS has
been asserted (S0), the special sequence shown in Figure 3-20 applies. Instead of being
asserted on the next rising edge of clock, BG is delayed until the second rising edge
following its internal assertion.
3-18
G = Bus Grant
R = Bus Request Internal
A = Bus Grant Acknowledge Internal
T = Three-state Control to Bus Control Logic
X = Don't Care
Figure 3-17. Bus Arbitration Unit State Diagrams
RA
X
STATE 2
GT
R
XX
STATE 1
GT
GT
GT
(a) 3-Wire Bus Arbitration
(b) 2-Wire Bus Arbitration
RA
XA
RA
R
RA
MC68306 USER'S MANUAL
R
1
RA
STATE 3
STATE 0
R
GT
GT
GT
RA
GT
GT
RA
RA
R
RA
RA
R+A
XA
X
XX
R
1
STATE 4
GT
GT
GT
Notes:
RX
1. State machine will not change if
2. The address bus will be placed in
BUS ARBITRATION CONTROL.
the bus is S0 or S1. Refer to
the high-impedance state if T is
asserted and AS is negated.
RA
MOTOROLA
5.2.3.