MC68306 Motorola, MC68306 Datasheet - Page 62

• Manufacturer Part Number: MC68306
• Description: Integrated EC000 Processor
• Manufacturer: Motorola

The negation of BERR and HALT under several conditions is shown in Table 3-2. (DTACK
is assumed to be negated normally in all cases; for reliable operation, both DTACK and
BERR should be negated when address strobe is negated).
EXAMPLE A:
EXAMPLE B:
• = Signal is negated in this bus state.
3.7 ASYNCHRONOUS OPERATION
To achieve clock frequency independence at a system level, the bus can be operated in
an asynchronous manner. Asynchronous bus operation uses the bus handshake signals
to control the transfer of data. The handshake signals are AS, UDS, LDS , DTACK, BERR ,
and HALT. AS indicates the start of the bus cycle, and UDS and LDS signal valid data for
a write cycle. After placing the requested data on the data bus (read cycle) or latching the
data (write cycle), the slave device (memory or peripheral) asserts DTACK to terminate
the bus cycle. If no device responds or if the access is invalid, external control logic
asserts BERR , or BERR and HALT, to abort or retry the cycle. Figure 3-28 shows the use
of the bus handshake signals in a fully asynchronous read cycle. Figure 3-29 shows a fully
asynchronous write cycle.
3-30
Termination in
A system uses a watchdog timer to terminate accesses to unused address space. The
timer asserts BERR after timeout (case 3).
A system uses error detection on random-access memory (RAM) contents. The system
designer may:
Conditions of
Table 4-4
Bus Error
1. Delay DTACK until the data is verified. If data is invalid, return BERR and HALT
2. Delay DTACK until the data is verified. If data is invalid, return BERR at the same
Normal
Normal
Rerun
Rerun
simultaneously to retry the error cycle (case 5).
time as DTACK (case 3).
Control Signal
BERR
BERR
BERR
BERR
BERR
HALT
HALT
HALT
HALT
HALT
Table 3-2.
Negated on Rising
BERR
N
MC68306 USER'S MANUAL
•
•
•
•
•
•
•
•
Edge of State
or
or
or
or
or
and
HALT
none
N+2
•
•
•
•
•
•
Takes bus error trap.
Illegal sequence; usually traps to vector number 0.
Reruns the bus cycle.
May lengthen next cycle.
If next cycle is started, it will be terminated as a bus
error.
Negation Results
Results—Next Cycle
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