AD9992_07 AD [Analog Devices], AD9992_07 Datasheet
AD9992_07
Related parts for AD9992_07
AD9992_07 Summary of contents
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FEATURES 1.8 V AFETG core Internal LDO regulator and charge pump circuitry Compatibility with 1.8 V systems 24 programmable vertical clock outputs Correlated double sampler (CDS) with −3 dB, 0 dB, +3 dB, and +6 dB gain ...
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AD9992 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Digital Specifications ................................................................... 4 Analog Specifications................................................................... 5 Timing Specifications .................................................................. 6 Absolute Maximum Ratings............................................................ 7 Thermal ...
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SPECIFICATIONS Table 1. Parameter TEMPERATURE RANGE Operating Storage POWER SUPPLY VOLTAGE INPUTS AVDD (AFE Analog Supply) TCVDD (Timing Core Supply) CLIVDD (CLI Input Supply) RGVDD (RG, HL Driver) 1 HVDD1/HVDD2 ( Drivers) DVDD (Digital Logic) DRVDD (Parallel Data ...
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AD9992 DIGITAL SPECIFICATIONS IOVDD = 1 3.6 V, RGVDD = HVDD = 2 3 Table 2. Parameter LOGIC INPUTS (IOVDD) High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level ...
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ANALOG SPECIFICATIONS AVDD = 1 MHz, typical timing specifications, T CLI Table 3. Parameter CDS Allowable CCD Reset Transient CDS Gain Accuracy −3.0 dB CDS Gain 0 dB CDS Gain +3 dB CDS Gain +6 dB ...
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AD9992 TIMING SPECIFICATIONS pF, AVDD = DVDD = TCVDD = 1.8 V, DRVDD = 3 Table 4. Parameter MASTER CLOCK (See Figure 15) CLI Clock Period CLI High/Low Pulse Width Delay from CLI Rising ...
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ABSOLUTE MAXIMUM RATINGS Table 5. With Parameter Respect To AVDD AVSS TCVDD TCVSS HVDD1/HVDD2 HVSS1/HVSS2 RGVDD RGVSS DVDD DVSS DRVDD DRVSS IOVDD DVSS XVVDD DVSS CLIVDD TCVSS CP1P8 CPVSS RG Output RGVSS H1 to H8, HL Output HVSS1/HVSS2 Digital Outputs ...
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AD9992 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Table 7. Pin Function Descriptions Pin No. Mnemonic A1 GPO8 B2 GPO7 C2 GPO6 B1 GPO5 B4 GPO4 C1 GPO3 D2 GPO2 C3 GPO1 D3 SYNC RSTB E6 IOVDD ...
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Pin No. Mnemonic L3 XV19 K1 XV20 K2 XV21 K3 XV22 J3 XV23 H3 XV24 L4 DVDD K4 DVSS ...
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AD9992 Pin No. Mnemonic C7 CLIVDD C6 CLO C5 CLI B6 AVDD A6 CCDIN B5, A5 AVSS A4 REFT A3 REFB SDATA B3 SCK A9, G10, K5, J4, J5 DIO = digital input/output, DI ...
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TYPICAL PERFORMANCE CHARACTERISTICS 500 450 400 350 300 250 200 150 100 FREQUENCY (MHz) Figure 4. Power vs. Frequency (AVDD = TCVDD = DVDD = 1.8 V, All Other Supplies at 2.7 V, 3.0 ...
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AD9992 EQUIVALENT CIRCUITS AVDD R CCDIN AVSS Figure 8. CCDIN DVDD DATA THREE- STATE DVSS Figure 9. Digital Data Outputs DIGITAL INPUT AVSS DRVDD RG DOUT THREE-STATE DRVSS Rev Page IOVDD 330Ω ...
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TERMINOLOGY Differential Nonlinearity (DNL) An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value. Therefore, every code must have a finite width. No missing codes guaranteed to 12-bit resolution indicates ...
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AD9992 SYSTEM OVERVIEW Figure 12 shows the typical system block diagram for the AD9992 in master mode. The CCD output is processed by AD9992 AFE circuitry, which consists of a CDS, VGA, black level clamp, and ADC. The digitized pixel ...
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HIGH SPEED PRECISION TIMING CORE The AD9992 generates high speed timing signals using the flexible Precision Timing core. This core is the foundation for generating timing used for both the CCD and the AFE; it includes the reset gate RG, ...
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AD9992 H-Driver and RG Outputs In addition to the programmable timing positions, the AD9992 features on-chip output drivers for the RG, HL, and outputs. These drivers are powerful enough to drive the CCD inputs directly. The H-driver ...
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H1, H3 H2, H4 H5, H7 H6, H8 POSITION P[0] CLI RGr[0] RG H1r[ CCD SIGNAL SHP SHDLOC[0] SHD 1 DOUTPHASEP NOTES: 1. ALL SIGNAL EDGES ARE FULLY PROGRAMMABLE TO ANY OF THE 64 POSITIONS WITHIN ONE PIXEL ...
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AD9992 P[0] PIXEL PERIOD DCLK t OD DOUT NOTES 1. DATA OUTPUT (DOUT) AND DCLK PHASE ARE ADJUSTABLE WITH RESPECT TO THE PIXEL PERIOD. 2. WITHIN ONE CLOCK PERIOD, THE DATA TRANSITION CAN BE PROGRAMMED TO 64 DIFFERENT LOCATIONS. 3. ...
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HORIZONTAL CLAMPING AND BLANKING The horizontal clamping and blanking pulses of the AD9992 are fully programmable to suit a variety of applications. Individual control is provided for CLPOB, PBLK, and HBLK in the different regions of each field. This allows ...
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AD9992 HD 2 CLPOB 1 ACTIVE PBLK PROGRAMMABLE SETTINGS: 1 START POLARITY (CLAMP AND BLANK REGION ARE ACTIVE LOW). 2 FIRST TOGGLE POSITION. 3 SECOND TOGGLE POSITION CLPOB CLPMASKSTART1 = 6 Individual HBLK Patterns The ...
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HD HBLKTOGE1 HBLKTOGE2 BLANK HBLK BASIC HBLK PULSE IS GENERATED USING HBLKTOGE1 AND HBLKTOGE2 REGISTERS (HBLKALT = 0) Figure 24. Typical Horizontal Blanking Pulse Placement (HBLKMODE = 0) HD HBLK H1/H3/H5/H7 THE POLARITY OF H1/H3/H5/H7 DURING BLANKING IS PROGRAMMABLE (H2/H4/H6/H8 ...
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AD9992 Table 11. HBLK Pattern Registers Register Length Range HBLKMODE HBLK modes HBLKSTART 13b 0 to 8191 pixel location HBLKEND 13b 0 to 8191 pixel location HBLKLEN 13b 0 to 8191 pixels HBLKREP 13b 0 to ...
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Register Length Range HBLKALT_PAT2 even repeat area HBLKALT_PAT3 even repeat area HBLKALT_PAT4 even repeat area HBLKALT_PAT5 even repeat area HBLKALT_PAT6 ...
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AD9992 HBLK H1/H3 H2/H4 CREATE GROUPS OF TOGGLES COMMON IN ALL REPEAT AREAS REPEAT AREA 0 HBLKSTART HD HBLK HBLKSTARTA HBLKSTARTB H1 RA0H1REPA RA0H1REPB H2 HBLKSTART RA0H2REPA RA0H2REPB ...
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HBLK Mode 2 Operation HBLK Mode 2 allows more advanced HBLK pattern operation. If multiple areas of HCLK pulses that are unevenly spaced apart from one another are needed, HBLK Mode 2 can be used. Using a separate set of ...
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AD9992 OPTICAL BLACK HD CCD OUTPUT VERTICAL SHIFT SHP SHD H1/H3/H5/H7 H2/H4/H6/H8 HBLK PBLK CLPOB NOTES 1. PBLK ACTIVE (LOW) SHOULD NOT BE USED DURING CLPOB ACTIVE (LOW). VERTICAL TIMING GENERATION The AD9992 provides a flexible solution for generating vertical ...
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CREATE THE VERTICAL PATTERN GROUPS FOUR TOGGLE POSITIONS FOR EACH OUTPUT. XV1 XV2 XV3 VPAT0 XV23 XV24 XV1 XV2 XV3 VPAT1 XV23 XV24 USE THE MODE REGISTERS TO CONTROL WHICH FIELDS 4 ARE USED, AND IN WHAT ...
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AD9992 Vertical Pattern Groups (VPAT) The vertical pattern groups define the individual pulse patterns for each XV1 to XV24 output signal. Table 13 summarizes the registers available for generating each of the V-pattern groups. The first, second, third, and fourth ...
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VERTICAL SEQUENCES (VSEQ) The vertical sequences are created by selecting one of the V-pattern groups and adding repeats, start position, horizontal clamping, and blanking information. The V-sequences are programmed using the registers shown in Table 14. Figure 35 shows how ...
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AD9992 Table 14. Summary of V-Sequence Registers (see Table 10 and Table 11 for the CLPOB, PBLK, and HBLK Pattern Registers) Register Length Description HOLD 4b Use in conjunction with VMASK_EN. 1: HOLD function instead of FREEZE/RESUME function. VMASK_EN 4b ...
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Register Length Description VREPA_3 13b Number of repetitions for the V-Pattern Group A for third lines. VREPA_4 13b Number of repetitions for the V-Pattern Group A for fourth lines. VREPB_ODD 13b Number of repetitions for the V-Pattern Group B for ...
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AD9992 HD XV1 TO XV8 USE V-PATTERN GROUP A XV1 XV8 XV9, XV10 USE V-PATTERN GROUP B XV9 XV10 HD V-PATTERN GROUP A XV1 XV24 HD V-PATTERN GROUP A XV1 XV10 GROUP A REP 1 Group A/Group B/Group C/Group D ...
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V-patterns are not needed. Note that when CONCAT_GRP is enabled, Group A settings are used only for start position, polarity, length, and repetitions. All toggle positions for Group A, Group B, Group C, ...
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AD9992 V-PATTERN A XV1 XV2 XV3 XV23 VLENA NOTES 1. EACH SEGMENT MUST BE THE SAME LENGTH. VLENA = VLENB = VLENC = VLEND. Figure 39. Vertical Timing Divided Into Four Segments: VPATA, VPATB, VPATC, and VPATD HD COMBINED A ...
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Using the LASTREPLEN_EN The LASTREPLEN_EN register (Address 0x00, Bits [19:16] in the sequence registers) is used to enable a separate pattern length to be used in the final repetition of several pulse repetitions recommended that the LASTREPLEN_EN register ...
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AD9992 Vertical Masking Using FREEZE/RESUME Registers As shown in Figure 43 and Figure 44, the FREEZE/RESUME registers are used to temporarily mask the V-outputs. The pixel locations to begin the masking (FREEZE) and end the masking (RESUME) create an area ...
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Hold Area Using FREEZE/RESUME Registers The FREEZE/RESUME registers can also be used to create a hold area in which the V-outputs are temporarily held and later continued, starting at the point where they were held. As shown in Figure 45, ...
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AD9992 Special Pattern Insertion Additional flexibility is available using the SPC_PAT_EN registers, which allows a Group B, Group C, or Group D pattern to be inserted into a series of Group A repetitions. This feature is useful when a different ...
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Complete Field: Combining V-Sequences After the V-sequences are created, they are combined to create different readout fields. A field consists nine regions, and within each region, a different V-sequence can be selected. Figure 48 shows how the ...
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AD9992 SCP0 SCP1 VD REGION 0 REGION 1 HD XV1 TO XVN SEQ0 SEQ1 SGACTLINE1 VSG FIELD SETTINGS: 1. SEQUENCE CHANGE POSITIONS (SCP0 TO SCP8) DEFINE EACH OF THE NINE AVAILABLE REGIONS IN THE FIELD. 2. SEQ0 TO SEQ8 SELECT ...
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Multiplier Mode To generate very wide vertical timing pulses, a vertical region can be configured into a multiplier region. This mode uses the V-pattern registers in a slightly different manner. Multiplier mode can be used to support unusual CCD timing ...
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AD9992 Vertical Sensor Gate (Shift Gate) Patterns In an interline CCD, the vertical sensor gate (VSG) pulses are used to transfer the pixel charges from the light-sensitive image area into light-shielded vertical registers. From the light- shielded vertical registers, the ...
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MODE Registers The MODE registers are used to select the field timing of the AD9992. Typically, all of the field, V-sequence, and V-pattern information is programmed into the AD9992 at startup. During operation, the MODE registers allow the user to ...
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AD9992 REGISTER WRITE MODE FIELD NUMBER REGISTER WRITE MODE FIELD NUMBER EXAMPLE 1: TOTAL FIELDS = 3, FIRST FIELD = FIELD0, SECOND FIELD = FIELD1, THIRD FIELD = FIELD2 MODE SETTINGS: 0x2A = 0x3 0x2B = 0x820 0x2C = 0x0 ...
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VERTICAL TIMING EXAMPLE To better understand how AD9992 vertical timing generation is used, consider the example CCD timing chart in Figure 55. This example illustrates a CCD using a general 3-field readout technique. As described in the Complete Field: Combining ...
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AD9992 Figure 55. CCD Timing Example—Dividing Each Field into Regions Rev Page N– N–1 N– N–2 N– ...
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SHUTTER TIMING CONTROL The AD9992 supports the generation of electronic shuttering (SUBCK) and also features flexible general-purpose outputs (GPO) to control mechanical shuttering, CCD substrate bias switching, and strobe circuitry. In the following documentation, the terms sense gate (SG) and ...
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AD9992 Read After Exposure To read the CCD data after exposure, the SG should resume normal activity while the SUBCK remains null. By default, the AD9992 generates the VSG pulses in every field. When only a single exposure and a ...
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VD HD VSG SUBCK SUBCK PROGRAMMABLE SETTINGS: 1. PULSE POLARITY USING THE SUBCK_POL REGISTER. 2. NUMBER OF PULSES WITHIN THE FIELD USING THE SUBCKNUM REGISTER (SUBCKNUM = 3 IN THE ABOVE EXAMPLE). 3. PIXEL LOCATION OF PULSE WITHIN THE LINE ...
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AD9992 FIELD COUNTERS The AD9992 contains three field counters (primary, secondary, and mode). When these counters are active, they increment with each VD cycle. The mode counter is the field counter used with the mode register to control the vertical ...
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GENERAL-PURPOSE OUTPUTS (GPOS) The AD9992 provides programmable outputs to control a mechanical shutter, strobe/flash, the CCD bias select signal, or any other external component with general-purpose (GP) signals. Eight GP signals, with up to four toggles each, are available that ...
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AD9992 Table 23. GPO Registers Register Length Range GP1_PROTOCOL GP2_PROTOCOL GP3_PROTOCOL GP4_PROTOCOL GP5_PROTOCOL GP6_PROTOCOL GP7_PROTOCOL 3b ...
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Single-Field Toggles Single-field toggles occur in the next field only. There can four toggles in the field. The mode is set with GP_PROTOCOL equal to 1, and then the toggles are triggered in the next field by ...
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AD9992 RapidShot Sequences RapidShot technology provides continuous repetition of scheduled toggles. Preparation The GP toggle positions can be programmed any time prior to use. For example, 0x71 0x0004000 0x7A 0x000A001 0x7B 0x0002000 0x7C 0x000000F 0x7D 0x00C4002 0x7E 0x0004000 0x7F 0x00000B3 ...
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GP LOOK-UP TABLES (LUT) The AD9992 is equipped with a look-up table for each pair of consecutive GP signals when configured as outputs. GP1 is always combined with GP2, GP3 is always combined with GP4, GP5 is always combined with ...
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AD9992 COMPLETE EXPOSURE/READOUT OPERATION USING PRIMARY COUNTER AND GPO SIGNALS Figure 65 demonstrates a typical expose/read cycle while exercising the GPO signals. Using a 3-field CCD with an exposure time that is greater than one field but less than two ...
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Figure 65. Complete Exposure/Readout Operation Using Primary Counter and GPO Signals Rev Page AD9992 ...
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AD9992 MANUAL SHUTTER OPERATION USING ENHANCED SYNC MODES The AD9992 also supports an external signal to control exposure, using the SYNC input. Generally, the SYNC input is used as an asynchronous reset signal during master mode operation. When the enhanced ...
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SYNC VD FIELD 7 DESIGNATOR H4, RG, XV1 TO XV24 VSG, SUBCK NOTES 1. THE SYNC RISING EDGE RESETS VD/HD AND COUNTERS SYNC POLARITY IS PROGRAMMABLE USING SYNCPOL REGISTER (ADDR 0x13). 3. DURING SYNC ...
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AD9992 SYNC VD HD SCP XV1 TO XV24 SYNC REGISTERS ARE UPDATED HERE. NOTES 1. VD-UPDATED REGISTERS (FOR EXAMPLE, PRIMARY_ACTION) ARE DISABLED DURING THE SYNC INTERVAL. SYNC VD FIELD 5 DESIGNATOR 1 VDLEN 2 3 ...
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SYNC FIELD DESIGNATOR V-OUTPUTS MSHUT VSUB DRAFT 1 SEE THE SHUTTER OPERATION IN SLR MODE SECTION. 2 SEE THE SHUTTER OPERATION IN SLR MODE SECTION. 3 SEE THE SHUTTER OPERATION IN SLR MODE SECTION. ...
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AD9992 ANALOG FRONT END DESCRIPTION AND OPERATION DC RESTORE 1.2V SHP SHD 1 S1 0.1µF CCDIN CDS –3dB, 0dB, +3dB, +6dB 1 S2 CDS GAIN REGISTER PBLK DOUTPHASE SHP SHD PRECISION CLI TIMING GENERATION NORMALLY CLOSED; S2 ...
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Variable Gain Amplifier The VGA stage provides a gain range of approximately dB, programmable with 10-bit resolution through the serial digital interface. A gain needed to match input signal ...
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AD9992 POWER-UP SEQUENCE FOR MASTER MODE When the AD9992 is powered up, the following sequence is recommended (refer to Figure 74 for each step). A SYNC signal is required for master mode operation external SYNC pulse is not ...
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Table 26. Power-Up Register Write Sequence Address Data Description 0x10 0x01 Resets all registers to default values 0x26 User-defined Standby3 vertical output polarities 0x20 to User-defined Horizontal, vertical, shutter timing 0xFFF 0xD8 0x888 Configures start-up register 0x00 0x04 Powers up ...
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AD9992 VD t VDHD HD t HDCLI CLI t HDCLO CLO SHPLOC INTERNAL SHDLOC INTERNAL HD INTERNAL H-COUNTER (PIXEL COUNTER) NOTES: 1. EXTERNAL HD FALLING EDGE IS LATCHED BY CLI RISING EDGE, THEN ...
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VD HD H-COUNTER – – 34 (PIXEL COUNTER) NOTES 1. TOGGLE POSITIONS CANNOT BE PROGRAMMED WITHIN 36 PIXELS OF PIXEL 0 LOCATION H-COUNTER (PIXEL COUNTER) ...
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AD9992 Table 27. Standby Mode Operation (Standby Polarities for XV, XSUBCK, GPO Outputs Are Programmable) I/O Block Standby3 (Default) AFE Off Timing Core Off CLO Oscillator Off CLO Low H1 High-Z H2 High-Z H3 High-Z H4 High-Z H5 High-Z H6 ...
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CIRCUIT LAYOUT INFORMATION The PCB layout is critical in achieving good image quality from the AD9992. All of the supply pins, particularly the AVDD, TCVDD, RGVDD, and HVDD supplies, must be decoupled to ground with good quality high frequency chip ...
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AD9992 MASTER CLOCK INPUT (3V LOGIC) ANALOG OUTPUT FROM CCD 3 SERIAL INTERFACE (FROM ASIC/DSP) GENERAL-PURPOSE OUTPUTS 8 GPO8 A1 GPO7 B2 GPO6 C2 GPO5 B1 GPO4 B4 GPO3 C1 GPO2 D2 GPO1 C3 RSTB EXTERNAL RESET IN E7 SYNC ...
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MASTER CLOCK INPUT (1.8V LOGIC) ANALOG OUTPUT FROM CCD 3 SERIAL INTERFACE (FROM ASIC/DSP) GENERAL-PURPOSE OUTPUTS 8 GPO8 A1 GPO7 B2 GPO6 C2 GPO5 B1 GPO4 B4 GPO3 C1 GPO2 D2 GPO1 C3 RSTB EXTERNAL RESET IN E7 SYNC EXTERNAL ...
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AD9992 SERIAL INTERFACE TIMING The internal registers of the AD9992 are accessed through a 3-wire serial interface. Each register consists of a 12-bit address and a 28-bit data-word. Both the 12-bit address and 28-bit data- word are written starting with ...
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LAYOUT OF INTERNAL REGISTERS The AD9992 address space is divided into two register areas, as illustrated in Figure 85. In the first address space, Address 0x00 to Address 0xFF contain the registers for the AFE, miscellaneous, VD/HD, I/O and CP, ...
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AD9992 UPDATING NEW REGISTER VALUES The AD9992 internal registers are updated at different times, depending on the particular register. Table 28 summarizes the four register update types: SCK, VD, SG-Line, and SCP. Tables in the Complete Register Listing section also ...
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COMPLETE REGISTER LISTING When an address contains fewer than 28 data bits, all remaining bits must be written as 0s. Table 29. AFE Registers Data Default Update Address Bits Value Type 0x00 [1:0] 3 SCK [2] 1 [3] 0 [4] ...
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AD9992 Data Default Update Address Bits Value Type [2] 0 [3] 0 [4] 0 [5] 1 [6] 1 [7] 0 [12:8] 0 [13] 0 [14] 0 0x14 [0] 0 SCK 0x15 [0] 0 SCK 0x16 [27:0] 0 SCK 0x17 [12:0] ...
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Table 32. I/O and Charge Pump Registers Data Default Update Address Bits Value Type 0x23 [0] 0 SCK [1] 0 [2] 0 [3] 0 [4] 0 [5] 0 [6] 0 [9:7] 1 0x24 [0] 0 SCK [1] 1 [2] 0 ...
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AD9992 Table 33. Memory Configuration and MODE Registers Address Data Bits Default Value 0x28 [4:0] 0 [9:5] 0 0x2A [2:0] 0 0x2B [4:0] 0 [9:5] 0 [14:10] 0 [19:15] 0 [24:20] 0 0x2C [4:0] 0 [9:5] 0 Table 34. Timing ...
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Default Address Data Bits Value [6:4] 1 [10:8] 1 [14:12] 1 [18:16] 1 [22:20] 1 0x36 [2:0] 1 [6:4] 1 [10:8] 1 [14:12] 1 0x37 [5:0] 0 [11:6] 20 [17:12] 10 0x38 [5:0] 0 [11:6] 20 [12] 0 [14:13] 0 ...
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AD9992 Default Address Data Bits Value [13:6] 0 0x71 [12:0] 0 [24:13] 0 [27:25] 0 0x72 [12:0] 0 [13] 0 [26:14] 0 [27] 0 0x73 [2:0] 0 [5:3] 0 [8:6] 0 [11:9] 0 [14:12] 0 [17:15] 0 [20:18] 0 [23:21] ...
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Default Address Data Bits Value [10] 1 [11] 1 [12] 1 [13] 1 [14] 1 [15] 1 [23:16] 0 [24] 0 [25] 0 [26] 0 [27] 0 0x79 [7:0] 0 [11:8] { [15:12] { ...
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AD9992 Default Address Data Bits Value 0x81 [12:0] 0 [25:13] 0 0x82 [12:0] 0 [25:13] 0 0x83 [12:0] 0 [25:13] 0 0x84 [12:0] 0 [25:13] 0 0x85 [12:0] 0 [25:13] 0 0x86 [12:0] 0 [25:13] 0 0x87 [12:0] 0 [25:13] ...
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Default Address Data Bits Value 0x8F [12:0] 0 [25:13] 0 0x90 [12:0] 0 [25:13] 0 0x91 [12:0] 0 [25:13] 0 0x92 [12:0] 0 [25:13] 0 0x93 [12:0] 0 [25:13] 0 0x94 [12:0] 0 [25:13] 0 0x95 [12:0] 0 [25:13] 0 ...
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AD9992 Default Address Data Bits Value 0x9D [12:0] 0 [25:13] 0 0x9E [12:0] 0 [25:13] 0 0x9F [12:0] 0 [25:13] 0 0xA0 [12:0] 0 [25:13] 0 0xA1 [12:0] 0 [25:13] 0 0xA2 [12:0] 0 [25:13] 0 0xA3 [12:0] 0 [25:13] ...
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Default Address Data Bits Value [2] 0 [3] 0 Table 38. Update Control Registers Data Default Address Bits Value Update 0xB0 [15:0] 1803 SCK 0xB1 [15:0] E7FC SCK 0xB2 [15:0] F8FD SCK 0xB3 [15:0] 0702 SCK 0xB4 [15:0] FFF9 SCK ...
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AD9992 Table 40. V-Pattern Group (VPAT) Register Map Address Data Bits Default Value 0x00 [12:0] X [25:13] X 0x01 [12:0] X [25:13] X 0x02 [12:0] X [25:13] X 0x03 [12:0] X [25:13] X 0x04 [12:0] X [25:13] X 0x05 [12:0] ...
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Address Data Bits Default Value 0x19 [12:0] X [25:13] X 0x1A [12:0] X [25:13] X 0x1B [12:0] X [25:13] X 0x1C [12:0] X [25:13] X 0x1D [12:0] X [25:13] X 0x1E [12:0] X [25:13] X 0x1F [12:0] X [25:13] X ...
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AD9992 Table 41. V-Sequence (VSEQ) Registers Data Default Update Address Bits Value Type 0x00 [0] X SCP [1] X [5:2] X [9:6] X [13:10] X [15:14] X [19:16] X [23:20] X [25:24] X 0x01 [12:0] X SCP [25:13] X 0x02 ...
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Data Default Update Address Bits Value Type 0x09 [4:0] X SCP [9:5] X [14:10] X [19:15] X 0x0A [12:0] X SCP [25:13] X 0x0B [12:0] X SCP [25:13] X 0x0C [12:0] X SCP [25:13] X 0x0D [12:0] X SCP [25:13] ...
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AD9992 Data Default Update Address Bits Value Type 0x1F [12:0] X SCP [25:13] X 0x20 [12:0] X SCP [13] X [14] X [17:15] X 0x21 [2:0] X SCP [6:4] X [10:8] X [14:12] X [18:16] X [22:20] X 0x22 [12:0] ...
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Data Default Update Address Bits Value Type 0x02 [12: [14:13] X [16:15] X [18:17] X [20:19] X [22:21] X [24:23] X [25] 0x03 [12: [25:13] X 0x04 [12: [25:13] X 0x05 [12: ...
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AD9992 OUTLINE DIMENSIONS BALL A1 PAD CORNER ORDERING GUIDE Model Temperature Range 1 AD9992BBCZ –25°C to +85°C 1 AD9992BBCZRL –25°C to +85° RoHS Compliant Part. ©2006–2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are ...