AD9992_07 AD [Analog Devices], AD9992_07 Datasheet - Page 18

• Manufacturer Part Number: AD9992_07
• Description: 12-Bit CCD Signal Processor with Precision Timing Generator
• Manufacturer: AD [Analog Devices]

AD9992
(INTERNAL)
(INTERNAL)
ADC DOUT
CCDIN
DCLK
DOUT
SHD
CLI
t
CLIDLY
NOTES
1. TIMING VALUES SHOWN ARE SHDLOC = 0, WITH DCLKMODE = 0.
2. HIGHER VALUES OF SHD AND/OR DOUT PHASE SHIFTS DOUT TRANSITION TO THE RIGHT, WITH RESPECT TO CLI LOCATION.
3. RECOMMENDED VALUE FOR DOUT PHASE IS TO USE SHPLOC OR UP TO 15 EDGES FOLLOWING SHPLOC.
N – 17
N – 17
N
SAMPLE PIXEL N
PERIOD
NOTES
1. DATA OUTPUT (DOUT) AND DCLK PHASE ARE ADJUSTABLE WITH RESPECT TO THE PIXEL PERIOD.
2. WITHIN ONE CLOCK PERIOD, THE DATA TRANSITION CAN BE PROGRAMMED TO 64 DIFFERENT LOCATIONS.
3. DCLK CAN BE INVERTED WITH RESPECT TO DOUT BY USING THE DCLKINV REGISTER.
N – 16
PIXEL
DOUT
N + 1
DCLK
N – 16
t
DOUTINH
N – 15
N + 2
N – 15
P[0]
N – 14
N + 3
N – 14
t
Figure 20. Digital Output Phase Adjustment Using DOUTPHASEP Register
OD
N – 13
N + 4
N – 13
N – 12
N + 5
N – 12
P[16]
Figure 21. Digital Data Output Pipeline Delay
N – 11
N + 6
N – 11
N – 10
PIPELINE LATENCY = 16 CYCLES
N + 7
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N – 10
N – 9
N + 8
P[32]
N – 9
N – 8
N + 9
N – 8
N + 10
N – 7
N – 7
N + 11
N – 6
P[48]
N – 6
N + 12
N – 5
N – 5
N + 13
N – 4
N – 4
P[64] = P[0]
N + 14
N – 3
N – 3
N + 15
N – 2
N – 2
N + 16
N – 1
N – 1
N + 17
N
N
N + 1
N + 1