AD9992_07 AD [Analog Devices], AD9992_07 Datasheet - Page 42

• Manufacturer Part Number: AD9992_07
• Description: 12-Bit CCD Signal Processor with Precision Timing Generator
• Manufacturer: AD [Analog Devices]

AD9992
Vertical Sensor Gate (Shift Gate) Patterns
In an interline CCD, the vertical sensor gate (VSG) pulses are
used to transfer the pixel charges from the light-sensitive image
area into light-shielded vertical registers. From the light-
shielded vertical registers, the image is clocked out line-by-line
using the vertical transfer pulses (XV signals) in conjunction
with the high speed horizontal clocks. The AD9992 has 24
vertical signals, and each signal can be assigned as a VSG pulse
instead of an XV pulse.
Table 19 summarizes the VSG control registers, which are mostly
located in the field registers space (see Table 17). The VSGSELECT
register (Address 0x1C in the fixed address space) determines
which vertical outputs are assigned as VSG pulses. When a signal
is selected to be a VSG pulse, only the starting polarity and two of
the V-pattern toggle positions are used. The VSGPATSEL register
in the sequence registers is used to assign either XVTOG1 and
XVTOG2 or XVTOG3 and XVTOG4 to the VSG signal.
Table 19. VSG Control Registers (Also see Field Registers in Table 17)
Register
VSGSELECT
(Located in Fixed
Address Space, 0x1C)
VSGPATSEL
SGMASK
SGACTLINE1
SGACTLINE2
VSG PATTERN
VD
HD
PROGRAMMABLE SETTINGS FOR EACH PATTERN:
1
2
3
4
START POLARITY OF PULSE (FROM VPOL IN SEQUENCE REGISTERS).
FIRST TOGGLE POSITION (FROM V-PATTERN REGISTERS).
SECOND TOGGLE POSITION (FROM V-PATTERN REGISTERS).
ACTIVE LINE FOR VSG PULSES WITHIN THE FIELD (FROM FIELD REGISTERS).
Length
24b
24b
24b
13b
13b
Range
High/low
High/low
High/low, each VSG
0 to 8191 line number
0 to 8191 line number
Figure 51. Vertical Sensor Gate Pulse Placement
Rev. C | Page 42 of 92
Description
Selection of VSG signals from XV signals. Set to 1 to make signal a VSG.
When VSG signal is selected using the VSGSELECT register, VSGPATSEL
selects which V-pattern toggle positions are used. When set to 0, Toggle 1
and Toggle 2 are used. When set to 1, Toggle 3 and Toggle 4 are used.
[0]: XV1 selection (0 = use XVTOG1, XVTOG2; 1 = use XVTOG3, XVTOG4).
[1]: XV2 selection.
…
[23]: XV24 selection.
Set high to mask each individual VSG output.
Selects the line in the field where the VSG signals are active.
Selects a second line in the field to repeat the VSG signals. If not used,
set this equal to SGACTLINE1 or to the maximum value.
[0]: XV1 selection (0 = XV pulse; 1 = VSG pulse).
[1]: XV2 selection.
…
[23]: XV24 selection.
[0]: XV1 mask.
…
[23]: XV24 mask.
Note that only two of the four V-pattern toggle positions are
available when a vertical signal is selected to be a VSG pulse.
The SGACTLINE1 and SGACTLINE2 registers are used to
select which line in the field is the VSG line. The VSG active
line location is used to reference when the substrate clocking
(SUBCK) signal begins to operate in each field. For more
information, see the Substrate Clock Operation (SUBCK)
section.
Also located in the field registers, the SGMASK register selects
which individual VSG pulses are active in a given field. Therefore,
all SG patterns to be preprogrammed into the V-pattern registers
and the appropriate pulses for the different fields can be enabled
separately.
4
1
2
3