AD9992_07 AD [Analog Devices], AD9992_07 Datasheet - Page 78

• Manufacturer Part Number: AD9992_07
• Description: 12-Bit CCD Signal Processor with Precision Timing Generator
• Manufacturer: AD [Analog Devices]

AD9992
Table 33. Memory Configuration and MODE Registers
Address
0x28
0x2A
0x2B
0x2C
Table 34. Timing Core Registers
Address
0x30
0x31
0x32
0x33
0x34
0x35
Data Bits
[4:0]
[9:5]
[2:0]
[4:0]
[9:5]
[14:10]
[19:15]
[24:20]
[4:0]
[9:5]
Data Bits
[5:0]
[13:8]
[16]
[5:0]
[13:8]
[16]
[5:0]
[13:8]
[16]
[5:0]
[13:8]
[16]
[0]
[1]
[2]
[3]
[7:4]
[2:0]
Default
Value
0
20
1
0
20
1
0
20
1
0
10
1
0
0
0
4
Default Value
0
0
0
0
0
0
0
0
0
0
0
1
Update
Type
SCK
SCK
SCK
SCK
SCK
SCK
Update Type
SCK
SCK
SCK
SCK
Mnemonic
H1POSLOC
H1NEGLOC
H1POL
H2POSLOC
H2NEGLOC
H2POL
HLPOSLOC
HLNEGLOC
HLPOL
RGPOSLOC
RGNEGLOC
RGH2POL
H1HBLKRETIME
H2HBLKRETIME
HLHBLKRETIME
HL_HBLK_EN
HCLK_WIDTH
H1DRV
Rev. C | Page 78 of 92
Mnemonic
VPATNUM
SEQNUM
MODE
FIELD0
FIELD1
FIELD2
FIELD3
FIELD4
FIELD5
FIELD6
Description
H1 rising edge location.
H1 falling edge location.
H1 polarity control:
0: Inverse of Figure 19.
1: No inversion.
H2 rising edge location (H5 in HCLK Mode 3).
H2 falling edge location (H5 in HCLK Mode 3).
H2 polarity (H5 in HCLK Mode 3):
0: Inverse of Figure 19.
1: No inversion.
HL rising edge location.
HL falling edge location.
HL polarity control:
0: Inverse of Figure 19.
1: No inversion.
RG rising edge location.
RG falling edge location.
RG polarity control:
0: Inverse of Figure 19.
1: No inversion.
Retime H1, H2, HL HBLK to the internal clock:
0: No retime.
1: Retime.
Recommended setting is retime enabled (1). Setting to 1
adds one cycle delay to programmed HBLK positions.
Enable HBLK for HL output:
0: Disable.
1: Enable.
Enables wide H-clocks during HBLK interval. Set to 0 to
disable.
H1 drive strength:
0: Off.
1: 4.3 mA.
2: 8.6 mA.
3: 12.9 mA.
4: 4.3 mA.
5: 8.6 mA.
6: 12.9 mA.
7: 17.2 mA.
Description
Total number of V-pattern groups.
Total number of V-sequences.
Total number of fields in MODE.
Selected first field in MODE.
Selected second field in MODE.
Selected third field in MODE.
Selected fourth field in MODE.
Selected fifth field in MODE.
Selected sixth field in MODE.
Selected seventh field in MODE.