AD9992_07 AD [Analog Devices], AD9992_07 Datasheet - Page 17

• Manufacturer Part Number: AD9992_07
• Description: 12-Bit CCD Signal Processor with Precision Timing Generator
• Manufacturer: AD [Analog Devices]

Digital Data Outputs
The AD9992 data output and DCLK phase are programmable
using the DOUTPHASE registers (Address 0x38, Bits [11:0]).
DOUTPHASEP (Bits [5:0]) selects any edge location from 0 to
63, as shown in Figure 20. DOUTPHASEN (Bits [11:6]) does
not actually program the phase of the data outputs but is used
internally and should always be programmed to a value of
DOUTPHASEP plus 32 edges. For example, if DOUTPHASEP
is set to 0, DOUTPHASEN should be set to 32 (0x20).
DOUTPHASEP
NOTES:
1. ALL SIGNAL EDGES ARE FULLY PROGRAMMABLE TO ANY OF THE 64 POSITIONS WITHIN ONE PIXEL PERIOD.
2. CERTAIN POSITIONS SHOULD BE AVOIDED FOR EACH SIGNAL, SHOWN ABOVE AS INHIBIT REGIONS.
3. IF A SETTING IN THE INHIBIT REGION IS USED, AN UNSTABLE PIXEL SHIFT CAN OCCUR IN THE HBLK LOCATION OR AFE PIPELINE.
4. THE t
5. THE t
6. THE t
TYPICAL POSITIONS FOR EACH SIGNAL ARE SHOWN. HCLK MODE 1 IS SHOWN.
H1HBLK MASKING POLARITY.
POSITION
SIGNAL
SHPINH
SHDINH
SHDINH
CCD
SHD
SHP
CLI
RG
H1
H2
AREA FROM 50 TO 62 ONLY APPLIES IN SLAVE MODE.
AREA CAN ALSO BE CHANGED TO A t
AREA WLL APPLY TO EITHER H1 RISING OR FALLING EDGE, DEPENDING ON THE VALUE OF THE
SHDLOC[0]
RGr[0]
H1r[0]
P[0]
H1, H3
H2, H4
H5, H7
H6, H8
1
t
DOUTINH
1
H1 TO H8 PROGRAMMABLE EDGES:
1
2
3
4
3
H1 RISING EDGE.
H1 FALLING EDGE.
H5 RISING EDGE.
H5 FALLING EDGE.
Figure 19. High Speed Timing Default Locations
12
RGf[16]
P[16]
2
Figure 18. HCLK Mode 3 Operation
t
S2
4
SHPINH
Rev. C | Page 17 of 92
t
SHDINH
AREA IF THE H1HBLKRETIME BIT = 1.
SHPLOC[32]
H1f[32]
P[32]
Normally, the DOUT and DCLK signals track in phase, based
on the contents of the DOUTPHASE registers. The DCLK output
phase can also be held fixed with respect to the data outputs by
changing the DCLKMODE register high (Address 0x38, Bit 12). In
this mode, the DCLK output remains at a fixed phase equal to a
delayed version of CLI while the data output phase is still
programmable.
The pipeline delay through the AD9992 is shown in Figure 21.
After the CCD input is sampled by SHD, there is a 16-cycle
delay until the data is available.
P[48]
t
S1
48
t
t
SHDINH
SHPINH
P[64] = P[0]
63
AD9992