AD9992_07 AD [Analog Devices], AD9992_07 Datasheet - Page 38

• Manufacturer Part Number: AD9992_07
• Description: 12-Bit CCD Signal Processor with Precision Timing Generator
• Manufacturer: AD [Analog Devices]

AD9992
Special Pattern Insertion
Additional flexibility is available using the SPC_PAT_EN registers,
which allows a Group B, Group C, or Group D pattern to be
inserted into a series of Group A repetitions. This feature is
useful when a different pattern is needed at the start, end, or
middle of a sequence.
Figure 46 shows an example of a sweep region using VPATA
with multiple repetitions where a single repetition of VPATB has
XV1 TO XV24
XV1
HD
VD
HD
REGISTER SETTINGS:
SPC_PAT_EN[0] = 1
VREPA = N
VREPB = 4
NOTES
1. VSTARTB MUST BE SET EQUAL TO VSTARTA.
V-PATTERN A
LINE 0
REP 1
REGION 0
LINE 1
REP 2
DESCRIPTION:
V-PATTERN B IS USED AS SPECIAL PATTERN
TOTAL NUMBER OF REPS USED FOR SEQUENCE (N REPS)
REP 4 USES V-PATTERN B INSTEAD OF V-PATTERN A
SCP1
Figure 47. Example of Special Pattern Insertion, Detail
Figure 46. Example of Special Pattern Insertion
REP 3
LINE 2
PATTERN B INSERTED DURING PATTERN A REPETITIONS
V-PATTERN B
Rev. C | Page 38 of 92
REGION 1: SWEEP REGION
REP 4
been added into the middle of the sequence. Figure 47 shows more
detail on how to set the registers to achieve the desired timing.
Note that VREPB is used to specify which repetition number
has the special pattern inserted instead of VPATA. VPATB
always has priority over VPATC or VPATD if more than one
SPC_PAT_EN bit is enabled (SPC_PAT_EN [0] has priority).
V-PATTERN A
REP 5
LINE 24
SCP2
REP N
LINE 25
REGION 2