AD9992_07 AD [Analog Devices], AD9992_07 Datasheet - Page 85
AD9992_07
Manufacturer Part Number
AD9992_07
Description
12-Bit CCD Signal Processor with Precision Timing Generator
Manufacturer
AD [Analog Devices]
Datasheet
1.AD9992_07.pdf
(92 pages)
- Current page: 85 of 92
- Download datasheet (2Mb)
Address
Table 38. Update Control Registers
Address
0xB0
0xB1
0xB2
0xB3
0xB4
0xB5
Table 39. Extra Registers
Address
0xD4
0xD7
0xD8
Data
Bits
[0]
[1]
[9:2]
[0]
[1]
[27:0]
Data
Bits
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
Data Bits
[2]
[3]
Default
Value
0
0
0
0
0
0
Default
Value
1803
E7FC
F8FD
0702
FFF9
0006
Default
Value
0
0
Update
SCK
SCK
SCK
SCK
SCK
SCK
Update
SCK
SCK
SCK
Update
Type
VD/SG
VD/SG
Mnemonic
TEST
GPO_INT_EN
TEST
TEST
XV24_SWAP
START
Mnemonic
AFE_UPDT_SCK
AFE_UPDT_VD
MISC_UPDT_SCK
MISC_UPDT_VD
VDHD_UPDT_SCK
VDHD_UPDT_VD
Mnemonic
SUBCKHP_TOG1_13
SUBCKHP_TOG2_13
Rev. C | Page 85 of 92
Enable SCK update of VDHD registers, Address 0x20 to Address 0x2F.
Test mode only. Set to 0.
Allow observation of internal signals at GPO5 to GPO8 outputs:
Test mode only. Set to 0.
Description
Each bit corresponds to one address location.
AFE_UPDT_SCK [0] = 1, update Address 0x00 on SL rising edge.
AFE_UPDT_SCK [1] = 1, update Address 0x01 on SL rising edge.
…
AFE_UPDT_SCK [15] = 1, update Address 0x0F on SL rising edge.
Each bit corresponds to one address location.
AFE_UPDT_VD [0] = 1, update Address 0x00 on VD rising edge.
AFE_UPDT_VD [1] = 1, update Address 0x01 on VD rising edge.
…
AFE_UPDT_VD [15] = 1, update Address 0x0F on VD rising edge.
Enable SCK update of miscellaneous registers, Address 0x10 to
Address 0x1F.
Enable VD update of miscellaneous registers, Address 0x10 to
Address 0x1F.
Enable VD update of VDHD registers, Address 0x20 to Address 0x2F.
Description
GPO5: OUTCONTROL.
GPO6: HBLK.
GPO7: CLPOB.
GPO8: PBLK.
Test mode only. Set to 0.
Set to 1 to change the V-driver output configuration so that XV15 is
output on the XV24 output pin. Useful with special vertical sequence
alternation mode when the XV24 register is reserved for pattern selection.
Recommended start-up register. Should be set to 0x888.
Description
Bit 13 for SUBCK HP Toggle 1. For 14-bit H-counter mode.
Bit 13 for SUBCK HP Toggle 2. For 14-bit H-counter mode.
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