DAC1408D650C1 NXP [NXP Semiconductors], DAC1408D650C1 Datasheet - Page 53

• Manufacturer Part Number: DAC1408D650C1
• Description: Dual 14-bit DAC up to 650 Msps 2, 4 or 8 interpolating
• Manufacturer: NXP [NXP Semiconductors]

NXP Semiconductors
Table 63.
Default settings are shown highlighted.
Table 64.
Default settings are shown highlighted.
Table 65.
Default settings are shown highlighted.
Table 66.
Default settings are shown highlighted.
Table 67.
Default settings are shown highlighted.
Table 68.
Default settings are shown highlighted.
Table 69.
Default settings are shown highlighted.
Table 70.
Default settings are shown highlighted.
DAC1408D650
Preliminary data sheet
Bit
7 to 0
Bit
7 to 0
Bit
7 to 0
Bit
7 to 0
Bit
7 to 0
Bit
7 to 0
Bit
3 to 0
Bit
6 to 4
2 to 0
Symbol
RST_EXT_FCLK[7:0]
Symbol
RST_EXT_DCLK[7:0]
Symbol
DCSMU_PREDIVCNT[7:0]
Symbol
PLL_CHARGE_TIME[7:0]
Symbol
PLL_RUNIN_TIME[7:0]
Symbol
CA_RUNIN_TIME[7:0]
Symbol
SET_VCM[3:0]
Symbol
SET_SYNC_VCOM[2:0]
SET_SYNC_LEVEL[2:0]
RST_EXT_FCLK register (address 04h) bit description
RST_EXT_DCLK register (address 05h) bit description
DCSMU_PREDIVCNT register (address 06h) bit description
PLL_CHARGETIME register (address 07h) bit description
PLL_RUN_IN_TIME register (address 08h) bit description
CA_RUN_IN_TIME register (address 09h) bit description
SET_VCM_VOLTAGE register (address 16h) bit description
SET_SYNC register (address 17h) bit description
DAC1408D; up to 650 Msps; 2×, 4× or 8× interpolating with JESD204A
All information provided in this document is subject to legal disclaimers.
Access
R/W
Access
R/W
Access
R/W
Access
R/W
Access
R/W
Access
R/W
Access
R/W
Access
R/W
R/W
Rev. 02 — 11 August 2010
Value
3Fh
Value
20h
Value
1Eh
Value
32h
Value
32h
Value
04h
Value
02h
Value
4h
3h
Description
specifies extension time reset_fclk in f
Description
Description
value used by dcsmu predivider (at f
Description
PLL charge time (at f
Description
Description
clock alignment run in time (at f
Description
set V
Description
set synchronization transmitter common-mode level
(see
(see
specifies extension time reset_dclk (in dclk-periods)
PLL run in time (at f
set synchronization transmitter output level swing
Table
Table
cm
voltage level (see
77)
78)
DAC1408D650
clk
clk
/predivcnt; sel_pd)
/predivcnt; start-up)
Table
clk
© NXP B.V. 2010. All rights reserved.
76)
/predivcnt)
clk
clk
)
periods
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