DAC1408D650C1 NXP [NXP Semiconductors], DAC1408D650C1 Datasheet - Page 95

DAC1408D650C1

Manufacturer Part Number

DAC1408D650C1

Description

Dual 14-bit DAC up to 650 Msps 2, 4 or 8 interpolating

Manufacturer

NXP [NXP Semiconductors]

Datasheet

1.DAC1408D650C1.pdf (98 pages)

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Table 59. PAGE_ADDRESS register (address 1Fh)

Table 60. Page 2 register allocation map . . . . . . . . . . . .51

Table 61. MAINCONTROL register (address 00h)

Table 62. JCLK_CNTRL register (address 03h)

Table 63. RST_EXT_FCLK register (address 04h)

Table 64. RST_EXT_DCLK register (address 05h) bit

Table 65. DCSMU_PREDIVCNT register (address 06h)

Table 66. PLL_CHARGETIME register (address 07h)

Table 67. PLL_RUN_IN_TIME register (address 08h)

Table 68. CA_RUN_IN_TIME register (address 09h)

Table 69. SET_VCM_VOLTAGE register (address 16h)

Table 70. SET_SYNC register (address 17h)

Table 71. TYPE_ID register (address 1Bh)

Table 72. DAC_VERSION register (address 1Ch)

Table 73. DIG_VERSION register (address 1Dh)

Table 74. JRX_ANA_VERSION register (address 1Eh)

Table 75. PAGE_ADDRESS register (address 1Fh)

Table 76. Lane common-mode voltage adjustment . . . . .55

Table 77. SYNC common-mode voltage adjustment . . . .55

Table 78. SYNC swing voltage adjustment . . . . . . . . . . .55

Table 79. Page 4 register allocation map . . . . . . . . . . . .56

Table 80. SR_DLP_0 register (address 00h)

Table 81. SR_DLP_1 register (address 01h)

Table 82. FORCE_LOCK register (address 02h)

Table 83. MAN_LOCK_LN_1_0 register (address 03h)

Table 84. MAN_LOCK_2_0 register (address 04h)

Table 85. CA_CNTRL register (address 05h)

Table 86. SCR-CNTRL register (address 06h)

DAC1408D650

Preliminary data sheet

bit description . . . . . . . . . . . . . . . . . . . . . . . . .50

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bit description . . . . . . . . . . . . . . . . . . . . . . . . .60

DAC1408D; up to 650 Msps; 2×, 4× or 8× interpolating with JESD204A

All information provided in this document is subject to legal disclaimers.

Rev. 02 — 11 August 2010

Table 87. ILA_CNTRL register (address 07h)

Table 88. FORCE_ALIGN register (address 08h)

Table 89. MAN_ALIGN_LN_0_1 register (address 09h)

Table 90. MAN_ALIGN_LN_2_3 register (address 0Ah)

Table 91. FA_ERR_HANDLING register (address 0Bh)

Table 92. SYNCOUT_MODE register (address 0Ch)

Table 93. LANE_POLARITY register (address 0Dh)

Table 94. LANE_SELECT register (address 0Eh)

Table 95. SOFT_RESET_SCRAMBLER register

Table 96. INIT_SCR_S15T8_LN0 register (address 11h)

Table 97. INIT_SCR_S7T1_LN0 (address 12h)

Table 98. INIT_SCR_S15T8_LN1 register (address 13h)

Table 99. INIT_SCR_S7T1_LN1 register (address 14h)

Table 100. INIT_SCR_S15T8_LN2 register (address 15h)

Table 101. INIT_SCR_S7T1_LN2 register (address 16h)

Table 102. INIT_SCR_S15T8_LN3 register (address 17h)

Table 103. INIT_SCR_S7T1_LN3 register (address 18h)

Table 104. INIT_ILA_BUFPTR_LN01 register

Table 105. INIT_ILA_BUFPTR_LN23 register

Table 106. ERROR_HANDLING register (address 1Bh)

Table 107. REINIT_CNTRL register (address 1Ch)

Table 108. PAGE_ADDRESS register (address 1Fh)

Table 109. Page 5 register allocation map . . . . . . . . . . . . 68

Table 110. ILA_MON_1_0 register (address 00h)

Table 111. ILA_MON_3_2 register (address 01h)

Table 112. ILA_BUF_ERR register (address 02h)

bit description . . . . . . . . . . . . . . . . . . . . . . . . . 61

bit description . . . . . . . . . . . . . . . . . . . . . . . . . 62

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(address 10h) bit description . . . . . . . . . . . . . . 64

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(address 19h) bit description . . . . . . . . . . . . . . 65

(address 1Ah) bit description . . . . . . . . . . . . . 65

bit description . . . . . . . . . . . . . . . . . . . . . . . . . 66

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bit description . . . . . . . . . . . . . . . . . . . . . . . . . 70

DAC1408D650

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DAC1408D650C1 NXP [NXP Semiconductors], DAC1408D650C1 Datasheet - Page 95

DAC1408D650C1

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