DAC1408D650C1 NXP [NXP Semiconductors], DAC1408D650C1 Datasheet - Page 87

• Manufacturer Part Number: DAC1408D650C1
• Description: Dual 14-bit DAC up to 650 Msps 2, 4 or 8 interpolating
• Manufacturer: NXP [NXP Semiconductors]

NXP Semiconductors
Table 191. LN3_CFG_3 register (address 13h) bit description
Default settings are shown highlighted.
Table 192. LN3_CFG_4 register (address 14h) bit description
Default settings are shown highlighted.
Table 193. LN3_CFG_5 register (address 15h) bit description
Default settings are shown highlighted.
Table 194. LN3_CFG_6 register (address 16h) bit description
Default settings are shown highlighted.
Table 195. LN3_CFG_7 register (address 17h) bit description
Default settings are shown highlighted.
Table 196. LN3_CFG_8 register (address 18h) bit description
Default settings are shown highlighted.
Table 197. LN3_CFG_9 register (address 19h) bit description
Default settings are shown highlighted.
Table 198. LN3_CFG_10 register (address 1Ah) bit description
Default settings are shown highlighted.
Table 199. LN3_CFG_11 register (address 1Bh) bit description
Default settings are shown highlighted.
DAC1408D650
Preliminary data sheet
Bit
7
4 to 0
Bit
7 to 0
Bit
4 to 0
Bit
7 to 0
Bit
7 to 6
4 to 0
Bit
4 to 0
Bit
4 to 0
Bit
7
4 to 0
Bit
7 to 0
Symbol
LN3_SCR
LN3_L[4:0]
Symbol
LN3_F[7:0]
Symbol
LN3_K[4:0]
Symbol
LN3_M[7:0]
Symbol
LN3_CS[1:0]
LN3_N[4:0]
Symbol
LN3_N'[4:0]
Symbol
LN3_S[4:0]
Symbol
LN3_HD
LN3_CF[4:0]
Symbol
LN3_RES1[7:0]
DAC1408D; up to 650 Msps; 2×, 4× or 8× interpolating with JESD204A
All information provided in this document is subject to legal disclaimers.
Access
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Access
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Access
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Rev. 02 — 11 August 2010
Value
-
-
Value
Value
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Value
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Value
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Value
-
Value
-
Value
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-
Value
-
-
-
Description
scrambling on
number of lanes
Description
Description
number of frames per multiframe
Description
number of converter per device
Description
number of control bits
Description
number of bits per sample
Description
number of samples per converter per frame cycle
Description
high density
number of control words per frame cycle
Description
lane 3 reserved field
number of octets per frame
converter resolution
DAC1408D650
© NXP B.V. 2010. All rights reserved.
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