PIC18F13K50-E/P MICROCHIP [Microchip Technology], PIC18F13K50-E/P Datasheet - Page 139
PIC18F13K50-E/P
Manufacturer Part Number
PIC18F13K50-E/P
Description
Manufacturer
MICROCHIP [Microchip Technology]
Datasheet
1.PIC18F13K50-EP.pdf
(414 pages)
- Current page: 139 of 414
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REGISTER 15-2:
© 2009 Microchip Technology Inc.
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6
bit 5
bit 4
bit 3-0
Note 1:
WCOL
R/W-0
2:
3:
In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by
writing to the SSPBUF register.
When enabled, these pins must be properly configured as input or output.
Bit combinations not specifically listed here are either reserved or implemented in I
WCOL: Write Collision Detect bit (Transmit mode only)
1 = The SSPBUF register is written while it is still transmitting the previous word
0 = No collision
SSPOV: Receive Overflow Indicator bit
SPI Slave mode:
1 = A new byte is received while the SSPBUF register is still holding the previous data. In case of over-
0 = No overflow
SSPEN: Synchronous Serial Port Enable bit
1 = Enables serial port and configures SCK, SDO, SDI and SS as serial port pins
0 = Disables serial port and configures these pins as I/O port pins
CKP: Clock Polarity Select bit
1 = Idle state for clock is a high level
0 = Idle state for clock is a low level
SSPM<3:0>: Synchronous Serial Port Mode Select bits
0101 = SPI Slave mode, clock = SCK pin, SS pin control disabled, SS can be used as I/O pin
0100 = SPI Slave mode, clock = SCK pin, SS pin control enabled
0011 = SPI Master mode, clock = TMR2 output/2
0010 = SPI Master mode, clock = F
0001 = SPI Master mode, clock = F
0000 = SPI Master mode, clock = F
SSPOV
R/W-0
(must be cleared by software)
flow, the data in SSPSR is lost. Overflow can only occur in Slave mode. The user must read the
SSPBUF, even if only transmitting data, to avoid setting overflow (must be cleared by software).
SSPCON1: MSSP CONTROL 1 REGISTER (SPI MODE)
W = Writable bit
‘1’ = Bit is set
SSPEN
R/W-0
PIC18F1XK50/PIC18LF1XK50
R/W-0
CKP
Preliminary
OSC
OSC
OSC
(1)
/64
/16
/4
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
(2)
SSPM3
R/W-0
(3)
SSPM2
R/W-0
x = Bit is unknown
SSPM1
R/W-0
2
C mode only.
DS41350C-page 137
SSPM0
R/W-0
bit 0
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