PIC18F13K50-E/P MICROCHIP [Microchip Technology], PIC18F13K50-E/P Datasheet - Page 157

• Manufacturer Part Number: PIC18F13K50-E/P
• Manufacturer: MICROCHIP [Microchip Technology]

REGISTER 15-7:
© 2009 Microchip Technology Inc.
bit 7
Legend:
R = Readable bit
-n = Value at POR
Master mode:
bit 7-0
10-Bit Slave mode — Most significant address byte:
bit 7-3
bit 2-1
bit 0
10-Bit Slave mode — Least significant address byte:
bit 7-0
7-Bit Slave mode:
bit 7-1
bit 0
R/W-0
ADD7
ADD<7:0>: Baud Rate Clock Divider bits
SCL pin clock period = ((ADD<7:0> + 1) *4)/F
Not used: Unused for Most Significant Address Byte. Bit state of this register is a “don’t care.” Bit pat-
tern sent by master is fixed by I
compared by hardware and are not affected by the value in this register.
ADD<9:8>: Two Most Significant bits of 10-bit address
Not used: Unused in this mode. Bit state is a “don’t care.”
ADD<7:0>: Eight Least Significant bits of 10-bit address
ADD<6:0>: 7-bit address
Not used: Unused in this mode. Bit state is a “don’t care.”
R/W-0
ADD6
SSPADD: MSSP ADDRESS AND BAUD RATE REGISTER (I
W = Writable bit
‘1’ = Bit is set
R/W-0
ADD5
PIC18F1XK50/PIC18LF1XK50
2
C specification and must be equal to ‘11110’. However, those bits are
R/W-0
ADD4
Preliminary
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
OSC
R/W-0
ADD3
R/W-0
ADD2
x = Bit is unknown
2
R/W-0
ADD1
C MODE)
DS41350C-page 155
R/W-0
ADD0
bit 0