PIC18F13K50-E/P MICROCHIP [Microchip Technology], PIC18F13K50-E/P Datasheet - Page 275

• Manufacturer Part Number: PIC18F13K50-E/P
• Manufacturer: MICROCHIP [Microchip Technology]

23.2
The MCLR pin provides a method for triggering an
external Reset of the device. A Reset is generated by
holding the pin low. These devices have a noise filter in
the MCLR Reset path which detects and ignores small
pulses.
The MCLR pin is not driven low by any internal Resets,
including the WDT.
In PIC18F1XK50/PIC18LF1XK50 devices, the MCLR
input can be disabled with the MCLRE Configuration
bit. When MCLR is disabled, the pin becomes a digital
input. See Section 9.1 “PORTA, TRISA and LATA
Registers” for more information.
23.3
A Power-on Reset pulse is generated on-chip
whenever V
allows the device to start in the initialized state when
V
To take advantage of the POR circuitry, tie the MCLR
pin through a resistor (1 kΩ to 10 kΩ) to V
eliminate external RC components usually needed to
create a Power-on Reset delay.
When the device starts normal operation (i.e., exits the
Reset condition), device operating parameters (volt-
age, frequency, temperature, etc.) must be met to
ensure operation. If these conditions are not met, the
device must be held in Reset until the operating
conditions are met.
POR events are captured by the POR bit of the RCON
register. The state of the bit is set to ‘0’ whenever a
POR occurs; it does not change for any other Reset
event. POR is not reset to ‘1’ by any hardware event.
To capture multiple events, the user must manually set
the bit to ‘1’ by software following any POR.
© 2009 Microchip Technology Inc.
DD
is adequate for operation.
Master Clear (MCLR)
Power-on Reset (POR)
DD
rises above a certain threshold. This
PIC18F1XK50/PIC18LF1XK50
DD
. This will
Preliminary
FIGURE 23-2:
Note 1: External Power-on Reset circuit is required
V
2: R < 40 kΩ is recommended to make sure that
3: R1 ≥ 1 kΩ will limit any current flowing into
DD
D
only if the V
The diode D helps discharge the capacitor
quickly when V
the voltage drop across R does not violate
the device’s electrical specification.
MCLR from external capacitor C, in the event
of MCLR/V
Electrostatic Discharge (ESD) or Electrical
Overstress (EOS).
V
DD
R
C
EXTERNAL POWER-ON
RESET CIRCUIT (FOR
SLOW V
DD
PP
R1
DD
power-up slope is too slow.
pin breakdown, due to
powers down.
DD
MCLR
PIC
DS41350C-page 273
POWER-UP)
®
MCU