PIC18F13K50-E/P MICROCHIP [Microchip Technology], PIC18F13K50-E/P Datasheet - Page 165

• Manufacturer Part Number: PIC18F13K50-E/P
• Manufacturer: MICROCHIP [Microchip Technology]

15.3.7
In I
reload value is placed in the SSPADD register
(Figure 15-17). When a write occurs to SSPBUF, the
Baud Rate Generator will automatically begin counting.
Once
transmission of the last data bit is followed by ACK), the
internal clock will automatically stop counting and the
SCL pin will remain in its last state.
FIGURE 15-17:
TABLE 15-3:
© 2009 Microchip Technology Inc.
Note 1:
2
C Master mode, the Baud Rate Generator (BRG)
the
48 MHz
48 MHz
48 MHz
40 MHz
40 MHz
40 MHz
16 MHz
16 MHz
16 MHz
4 MHz
4 MHz
4 MHz
The I
100 kHz) in all details, but may be used with care where higher rates are required by the application.
BAUD RATE
F
OSC
given
2
C interface does not conform to the 400 kHz I
I
2
C™ CLOCK RATE W/BRG
operation
BAUD RATE GENERATOR BLOCK DIAGRAM
SSPM<3:0>
SCL
is
complete
12 MHz
12 MHz
12 MHz
10 MHz
10 MHz
10 MHz
SSPM<3:0>
4 MHz
4 MHz
4 MHz
1 MHz
1 MHz
1 MHz
PIC18F1XK50/PIC18LF1XK50
F
CY
Reload
Control
(i.e.,
CLKOUT
Preliminary
Reload
Table 15-3 demonstrates clock rates based on
instruction cycles and the BRG value loaded into
SSPADD.
EQUATION 15-1:
2
BRG Down Counter
C specification (which applies to rates greater than
SSPADD<7:0>
BRG Value
0Ch
0Bh
1Fh
1Dh
18h
63h
09h
27h
02h
09h
00h
77h
F
SCL
=
----------------------------------------------
(
SSPADD
F
OSC
(2 Rollovers of BRG)
/2
F
OSC
+
400 kHz
400 kHz
333 kHz
312.5 kHz
DS41350C-page 163
1 MHz
1 MHz
400 kHz
100 kHz
100 kHz
308 kHz
100 kHz
100 kHz
1
F
) 4 ( )
SCL
(1)
(1)
(1)
(1)
(1)