PIC18F13K50-E/P MICROCHIP [Microchip Technology], PIC18F13K50-E/P Datasheet - Page 235
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PIC18F13K50-E/P
Manufacturer Part Number
PIC18F13K50-E/P
Description
Manufacturer
MICROCHIP [Microchip Technology]
Datasheet
1.PIC18F13K50-EP.pdf
(414 pages)
- Current page: 235 of 414
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19.3
The Power-Managed Sleep mode in the PIC18F1XK50/
PIC18LF1XK50 devices is identical to the legacy Sleep
mode offered in all other PIC
It is entered by clearing the IDLEN bit of the OSCCON
register and executing the SLEEP instruction. This shuts
down the selected oscillator (Figure 19-1) and all clock
source status bits are cleared.
Entering the Sleep mode from either Run or Idle mode
does not require a clock switch. This is because no
clocks are needed once the controller has entered
Sleep. If the WDT is selected, the LFINTOSC source
will continue to operate. If the Timer1 oscillator is
enabled, it will also continue to run.
When a wake event occurs in Sleep mode (by interrupt,
Reset or WDT time-out), the device will not be clocked
until the clock source selected by the SCS<1:0> bits
becomes ready (see Figure 19-2), or it will be clocked
from the internal oscillator block if either the Two-Speed
Start-up or the Fail-Safe Clock Monitor are enabled
(see Section 24.0 “Special Features of the CPU”). In
either case, the OSTS bit is set when the primary clock
is providing the device clocks. The IDLEN and SCS bits
are not affected by the wake-up.
FIGURE 19-1:
FIGURE 19-2:
© 2009 Microchip Technology Inc.
Peripheral
Program
Counter
OSC1
Clock
Clock
Sleep
CPU
CPU Clock
Note1: T
Peripheral
PLL Clock
Program
Sleep Mode
Counter
Output
OSC1
Clock
Q1
OST
Q2
PC
= 1024 T
Q3
Wake Event
Q4
TRANSITION TIMING FOR ENTRY TO SLEEP MODE
TRANSITION TIMING FOR WAKE FROM SLEEP (HSPLL)
OSC
Q1
; T
Q1
®
PLL
microcontroller devices.
T
OST (1)
= 2 ms (approx). These intervals are not shown to scale.
PIC18F1XK50/PIC18LF1XK50
PC
T
PLL
OSTS bit set
(1)
Preliminary
Q2 Q3 Q4 Q1 Q2
PC + 2
19.4
The Idle modes allow the controller’s CPU to be
selectively shut down while the peripherals continue to
operate. Selecting a particular Idle mode allows users
to further manage power consumption.
If the IDLEN bit is set to a ‘1’ when a SLEEP instruction is
executed, the peripherals will be clocked from the clock
source selected by the SCS<1:0> bits; however, the CPU
will not be clocked. The clock source status bits are not
affected. Setting IDLEN and executing a SLEEP instruc-
tion provides a quick method of switching from a given
Run mode to its corresponding Idle mode.
If the WDT is selected, the LFINTOSC source will con-
tinue to operate. If the Timer1 oscillator is enabled, it
will also continue to run.
Since the CPU is not executing instructions, the only
exits from any of the Idle modes are by interrupt, WDT
time-out, or a Reset. When a wake event occurs, CPU
execution is delayed by an interval of T
becomes ready to execute code. When the CPU
begins executing code, it resumes with the same clock
source for the current Idle mode. For example, when
waking from RC_IDLE mode, the internal oscillator
block will clock the CPU and peripherals (in other
words, RC_RUN mode). The IDLEN and SCS bits are
not affected by the wake-up.
While in any Idle mode or the Sleep mode, a WDT
time-out will result in a WDT wake-up to the Run mode
currently specified by the SCS<1:0> bits.
PC + 2
Q3 Q4 Q1 Q2
Idle Modes
PC + 4
Q3 Q4
Q1 Q2 Q3 Q4
DS41350C-page 233
PC + 6
CSD
while it
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