PIC18F13K50-E/P MICROCHIP [Microchip Technology], PIC18F13K50-E/P Datasheet - Page 22

• Manufacturer Part Number: PIC18F13K50-E/P
• Manufacturer: MICROCHIP [Microchip Technology]

PIC18F1XK50/PIC18LF1XK50
TABLE 2-2:
2.9
A Phase Locked Loop (PLL) circuit is provided as an
option for users who wish to use a lower-frequency
external oscillator or to operate at 32 MHz with the
HFINTOSC. The PLL is designed for an input
frequency from 4 MHz to 12 MHz. The PLL multiplies
its input frequency by a factor of four when the PLL is
enabled. This may be useful for customers who are
concerned with EMI, due to high-frequency crystals.
Two bits control the PLL: the PLLEN bit of the
CONFIG1H Configuration register and the SPLLEN bit
of the OSCTUNE register. The PLL is enabled when
the PLLEN bit is set and it is under software control
when the PLLEN bit is cleared.
TABLE 2-3:
2.10
The CPU Clock Divider allows the system clock to run
at a slower speed than the Low/Full Speed USB
module clock while sharing the same clock source.
Only the oscillator defined by the settings of the FOSC
bits of the CONFIG1H Configuration register may be
used with the CPU Clock Divider. The CPU Clock
Divider is controlled by the CPUDIV bits of the
CONFIG1L Configuration register. Setting the CPUDIV
bits will set the system clock to:
• Equal the clock speed of the USB module
• Half the clock speed of the USB module
• One third the clock speed of the USB module
• One fourth the clock speed of the USB module
For more information on the CPU Clock Divider, see
Figure 2-1 and Register 24-1 CONFIG1L.
DS41350C-page 20
Sleep/POR
Sleep/POR
Sleep/POR
Note:
PLLEN
1
0
0
4x Phase Lock Loop Frequency
Multiplier
CPU Clock Divider
The HFINTOSC may use the PLL when
the postscaler is set to 8 MHz and the
FOSC<3:0>
Configuration register are selected for
Internal Oscillator operation.
Switch From
EXAMPLES OF DELAYS DUE TO CLOCK SWITCHING
PLL CONFIGURATION
SPLLEN
bits of
x
1
0
the
PLL disabled
PLL enabled
PLL enabled
PLL Status
CONFIG1H
Preliminary
HFINTOSC
LFINTOSC
LP, XT, HS
Switch To
EC, RC
2.11
The USB module is designed to operate in two different
modes:
• Low Speed
• Full Speed
Because of timing requirements imposed by the USB
specifications, the Primary External Oscillator is
required for the USB module. The FOSC bits of the
CONFIG1H Configuration register must be set to either
External Clock (EC) High-power or HS mode with a
clock frequency of 6, 12 or 48 MHz.
2.11.1
For Low Speed USB operation, a 6 MHz clock is
required for the USB module. To generate the 6 MHz
clock, only 2 Oscillator modes are allowed:
• EC High-power mode
• HS mode
Table 2-4 shows the recommended Clock mode for
low-speed operation.
2.11.2
For full-speed USB operation, a 48 MHz clock is
required for the USB module. To generate the 48 MHz
clock, only 2 Oscillator modes are allowed:
• EC High-power mode
• HS mode
Table 2-5 shows the recommended Clock mode for full-
speed operation.
USB Operation
LOW SPEED OPERATION
FULL-SPEED OPERATION
Oscillator Warm-up Delay (T
© 2009 Microchip Technology Inc.
1024 clock cycles
Oscillator Delay
8 Clock Cycles
WARM
)