PIC18F13K50-E/P MICROCHIP [Microchip Technology], PIC18F13K50-E/P Datasheet - Page 85

• Manufacturer Part Number: PIC18F13K50-E/P
• Manufacturer: MICROCHIP [Microchip Technology]

TABLE 9-1:
© 2009 Microchip Technology Inc.
RA0/KAI0/D+/PGD
RA1/KAI1/D-/PGC
MCLR/V
KAI3
RA4/KAI4/AN3/
OSC2/CLKOUT
RA5/KAI5/OSC1/
CLKIN
Legend:
Note 1: RA0 and RA1 do not have corresponding TRISA bits. In Port mode, these pins are input only. USB data direction is
Pin
PP
2: RA3 does not have a corresponding TRISA bit. This pin is always an input regardless of mode.
/RA3/
DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level input/output;
x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
determined by the USB configuration.
PORTA I/O SUMMARY
Function
CLKOUT
MCLR
CLKIN
OSC2
OSC1
KAI0
PGD
KAI1
PGC
KAI3
KAI4
KAI5
RA0
RA1
RA3
RA4
AN3
RA5
V
D+
D-
PP
Setting
TRIS
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
1
1
1
x
x
0
1
1
x
x
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(2)
(1)
I/O
PIC18F1XK50/PIC18LF1XK50
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
XCVR USB bus differential plus line input (internal transceiver).
XCVR USB bus differential plus line output (internal transceiver).
XCVR USB bus differential minus line input (internal transceiver).
XCVR USB bus differential minus line output (internal transceiver).
Type
ANA
ANA
ANA
ANA
ANA
TTL
TTL
DIG
TTL
TTL
DIG
TTL
DIG
TTL
TTL
DIG
DIG
TTL
TTL
I/O
ST
ST
ST
ST
Preliminary
PORTA<0> data input; disabled when USB enabled.
Interrupt-on-pin change; disabled when USB enabled.
Serial execution data output for ICSP™.
Serial execution data input for ICSP™.
PORTA<1> data input; disabled when USB enabled.
Interrupt-on-pin change; disabled when USB enabled.
Serial execution clock output for ICSP™.
Serial execution clock input for ICSP™.
External Master Clear input; enabled when MCLRE Configuration bit is
set.
High-voltage detection; used for ICSP™ mode entry detection. Always
available, regardless of pin mode.
PORTA<3> data input; enabled when MCLRE Configuration bit is
clear; Programmable weak pull-up.
Interrupt-on-pin change
LATA<4> data output. Enabled in RCIO, INTIO2 and ECIO modes only.
PORTA<4> data input; Programmable weak pull-up. Enabled in RCIO,
INTIO2 and ECIO modes only.
Interrupt-on-pin change
A/D input channel 3. Default configuration on POR.
Main oscillator feedback output connection (XT, HS and LP modes).
System cycle clock output (F
modes.
LATA<5> data output. Disabled in external oscillator modes.
PORTA<5> data input. Disabled in external oscillator modes; Program-
mable weak pull-up.
Interrupt-on-pin change
Main oscillator input connection.
Main clock input connection.
OSC
Description
/4) in RC, INTIO1 and EC Oscillator
DS41350C-page 83