TMC211-PA20 TRINAMIC [TRINAMIC Motion Control GmbH & Co. KG.], TMC211-PA20 Datasheet - Page 27

• Manufacturer Part Number: TMC211-PA20
• Description: Micro Stepping Stepper Motor Controller / Driver with LIN Interface
• Manufacturer: TRINAMIC [TRINAMIC Motion Control GmbH & Co. KG.]

TMC211 DATASHEET (V. 1.04 / January 7, 2005)
6.5 Physical Address of the circuit
The circuit must be provided with a physical address in order to discriminate this circuit from other
ones on the LIN bus. This address is coded on seven bits, yielding the theoretical possibility of 128
different circuits on the same bus. It is a combination of four OTP memory bits (see 5.2.3 OTP Memory
Structure) and three hardwired address bits (pins HW0, HW1 and HW2). Pins HW0 and HW1 are 5V
digital inputs, whereas pin HW2 is compliant with a 12V level. HW2 must either be connected to Vbat
or ground. Pin HW2 uses the same principle to check whether it is connected to ground or Vbat like
the SWI input (see 5.1.9 External Switch).
The TCM211 supports broadcasting. When the <Broad> bit is set to zero, broadcasting is active and
each slave on the LIN bus will be addressed.
The amount of physical addresses can be expanded by using bit ADM. This bit allows for the following
expansion:
6.6 Electro Magnetic Compability
EMC behavior fulfills requirements defined by LIN specification rev. 1.3.
6.7 Error Status Register
The LIN interface implements a register containing an error status of the LIN communication. This
register is specified as follows:
Note:
Data Error Flag = Checksum error OR StopBit error OR Length error
Header Error Flag = Parity error OR Synch Field error
A GetFullStatus command will reset the error status register
Copyright © 2004-2005 TRINAMIC Motion Control GmbH & Co. KG
Not used
ADM
Bit7
0
1
Not used
HW0
AD6
PA0
Bit6
HW0
AD6
Not used
HW1
AD5
HW1
HW0
AD5
Bit5
Table 13: Physical Address Expansion
Table 14: LIN Error Status Register
Figure 16: Physical Slave Address
HW2
AD4
OTP_AD3
Not used
AD3
HW2
HW1
AD4
Bit4
OTP_AD2
AD2
OTP_AD1
Error Flag
Timeout
AD1
HW2
AD3
PA3
Bit3
OTP_AD0
AD0
Data Error
Physical address
OTP Memory
Hardwired Bits
AD2
Flag
PA2
PA3
Bit2
Error Flag
Header
AD1
PA1
PA2
Bit1
Bit Error
AD0
Flag
PA0
PA1
Bit0
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