FDC37N769_07 SMSC [SMSC Corporation], FDC37N769_07 Datasheet - Page 110

• Manufacturer Part Number: FDC37N769_07
• Description: 3.3V Super I/O Controller with Infrared Support for Portable Applications
• Manufacturer: SMSC [SMSC Corporation]

CR26
CR26 can only be accessed in the configuration state and after the CSR has been initialized to 26H.
value of this register after power up is 00H (Table 108). CR26 is used to select the DMA for the FDC (Bits 4 - 7) and
the Parallel Port (bits 0 - 3). Any unselected DMA Requset output (DRQ) is in tristate.
CR27
CR27 can only be accessed in the configuration state and after the CSR has been initialized to 27H.
value of this register after power up is 00H (Table 109). CR27 is used to select the IRQ for the FDC (Bits 4 - 7) and
the Parallel Port (bits 3 - 0). Any unselected IRQ output (registers CR27 - CR29) is in tristate.
CR28
CR28 can only be accessed in the configuration state and after the CSR has been initialized to 28H. The default
value of this register after power up is 00H. CR28 is used to select the IRQ for Serial Port 1 (bits 7 - 4) and for Serial
Port 2 (bits 3 - 0). Refer to the IRQ encoding for CR27 (Table 109). Any unselected IRQ output (registers CR27 -
CR29) is in tristate.
To properly share an IRQ between UART1 and UART2:
SMSC DS – FDC37N769
1.
2.
OUT2 bit
UART1
0
1
1
0
0
1
1
1
1
0
1
1
0
0
Configure UART1 to use the desired IRQ pin.
Set UART2 to 0FH i.e., set CR28.[3:0] = 1111b. This selects the share IRQ mechanism. Refer to Table
110, below.
UART1
Output State
UART1 IRQ
de-asserted
de-asserted
de-asserted
de-asserted
asserted
asserted
asserted
asserted
Z
Z
Z
Z
Z
Z
Table 108 - CR26: FDC and PP DMA Selection Register
Table 109 - CR27: FDC and PP IRQ Selection Register
D3-D0 or D7-D4
D3-D0 or D7-D4
OUT2 bit
Table 110 - UART Interrupt Operation
UART2
0000
0001
0010
0011
0100
0101
0110
0111
1000
DATASHEET
0
0
0
1
1
1
1
1
1
0
0
0
1
1
0000
0001
0010
0011
UART2
Output State
Page 110 of 137
UART2 IRQ
de-asserted
de-asserted
de-asserted
de-asserted
asserted
asserted
asserted
asserted
Z
Z
Z
Z
Z
Z
DMA SELECTED
IRQ SELECTED
Reserved
DMA_A
DMA_B
DMA_C
IRQ_A
IRQ_B
IRQ_C
IRQ_D
IRQ_E
IRQ_H
IRQ_F
None
None
Share
IRQ
Yes
Yes
Yes
Yes
Yes
No
No
No
No
No
No
No
No
No
Pin State
UART1
Z
1
0
Z
Z
1
1
0
0
Z
1
0
1
0
IRQ PINS
Pin State
UART2
Z
Z
Z
Z
Z
Z
Z
Z
1
0
1
0
1
0
The default
The default
Rev. 02-16-07