FDC37N769_07 SMSC [SMSC Corporation], FDC37N769_07 Datasheet - Page 60

• Manufacturer Part Number: FDC37N769_07
• Description: 3.3V Super I/O Controller with Infrared Support for Portable Applications
• Manufacturer: SMSC [SMSC Corporation]

Interrupt Pending, Bit 0
The Interrupt Pending bit can be used in either a hardwired prioritized or polled environment to indicate whether an
interrupt is pending. When bit 0 is a logic “0”, an interrupt is pending and the contents of the IIR may be used as a
pointer to the appropriate internal service routine. When bit 0 is a logic “1”, no interrupt is pending.
Interrupt ID, Bits 1 - 2
The Interrupt ID bits of the IIR are used to identify the highest priority interrupt pending as indicated by the Interrupt
Control Table (Table 52).
Time-Out, Bit 3
In non-FIFO mode, the Time-Out bit is a logic “0”. In FIFO mode the Time-Out bit is set along with bit 2 when a time-
out interrupt is pending.
Reserved, Bits 4 - 5
Bits 4 to 5 are RESERVED. Reserved bits cannot be written and return 0 when read.
FIFOs Enabled, Bits 6 - 7
The FIFOs Enabled bits are set when the FIFO CONTROL Register bit 0 equals 1.
SMSC DS – FDC37N769
MODE
ONLY
FIFO
BIT
3
0
0
0
1
0
BIT
2
0
1
1
1
0
IDENTIFICATION
INTERRUPT
REGISTER
BIT
1
0
1
0
0
1
BIT
0
1
0
0
0
0
Highest
Second
Second
Third
DATASHEET
PRIORITY
Table 52 - Interrupt Control
LEVEL
-
Page 60 of 137
INTERRUPT SET AND RESET FUNCTIONS
None
Receiver Line
Status
Received
Data
Available
Character
Time-out
Indication
Transmitter
Holding
Register
Empty
INTERRUPT
TYPE
None
Overrun Error,
Parity Error,
Framing Error
or Break
Interrupt
Receiver Data
Available
No Characters
Have Been
Removed
From or Input
to the RCVR
FIFO during
the last 4
Character
times and there
is at least 1
character in it
during this time
Transmitter
Holding
Register Empty
INTERRUPT
SOURCE
Reading the Line
Status Register
Read Receiver
Buffer or the FIFO
drops below the
trigger level.
Reading the
Receiver Buffer
Register
Reading the IIR
Register (if Source
of Interrupt) or
Writing the
Transmitter Holding
Register
RESET CONTROL
INTERRUPT
-
Rev. 02-16-07