FDC37N769_07 SMSC [SMSC Corporation], FDC37N769_07 Datasheet - Page 8

• Manufacturer Part Number: FDC37N769_07
• Description: 3.3V Super I/O Controller with Infrared Support for Portable Applications
• Manufacturer: SMSC [SMSC Corporation]

SMSC DS – FDC37N769
39-41,
35-38,
TQFP
19,50,
20,34,
46-49
51-54
26-32
PIN #
17,
42
43
44
95
97
94
33
22
25
55
98
14
8
Data Bus 0-
7
nI/O Read
nI/O Write
Address
Enable
Address
Bus
DMA
Request
A, B, C
nDMA
Acknowl-
edge
A, B, C
Terminal
Count
Interrupt
Request
A, C, D,
E, F, and H
Chip Select
Input
Reset
I/O Channel
Ready
(Note
nRead Disk
Data
nWrite
Gate
NAME
4
)
D0-D7
nIOR
nIOW
AEN
A0-A10
DRQ_A
DRQ_B
DRQ_C
nDACK_A
nDACK_B
nDACK_C
TC
IRQ_A
IRQ_C
IRQ_D
IRQ_E
IRQ_F
IRQ_H
nCS
RESET
IOCHRDY
nRDATA
nWGATE
SYMBOL
Table 1 - DESCRIPTION OF PIN FUNCTIONS
HOST PROCESSOR INTERFACE
DATASHEET
O12/OD12
O12/OD12
BUFFER TYPE PER PIN
FLOPPY DISK INTERFACE
BUFFER
TYPE
OD12
IO12
O12
PIN DESCRIPTION
IS
IS
IS
IS
IS
IS
IS
I
I
Page 8 of 137
This active low signal is issued by the host micropro-
The data bus connection used by the host
microprocessor to transmit data to and from the chip.
These pins are in a high-impedance state when not in
the output mode.
This active low signal is issued by the host micropro-
cessor to indicate an I/O read operation.
cessor to indicate an I/O write operation.
Active high Address Enable indicates DMA operations
on the host data bus.
appropriate address decodes.
These host address bits determine the I/O address to
be accessed during nIOR and nIOW cycles. These
bits are latched internally by the leading edge of nIOR
and nIOW. All internal address decodes use the full
A0 to A10 address bits.
These active high outputs are the DMA request for
byte transfers of data between the host and the chip.
These signals are cleared on the last byte of the data
transfer by the nDACK signal going low (or by nIOR
going low if nDACK was already low as in demand
mode).
These are active low inputs acknowledging the
request for a DMA transfer of data between the host
and the chip. These inputs enable the DMA read or
write internally.
This signal indicates that DMA data transfer is
complete. TC is only accepted when nDACK_x is
low. In AT and PS/2 model 30 modes, TC is active
high and in PS/2 mode, TC is active low.
Interrupt requests from a logical device or IRQIN are
output on one of the IRQA-H signals. Refer to the
configuration
information.
If EPP or ECP Mode is enabled this output is pulsed
low and released to allow sharing of interrupts.
This active low input serves as an external decoder
for address lines above A10.
This active high signal resets the chip and must be
valid for 500ns minimum. The effect on the internal
registers is described in the appropriate section. The
configuration registers are not affected by this reset.
This pin is pulled low to extend the read/write
command. IOCHRDY can used by the IRCC and by
the Parallel Port in EPP mode.
Raw serial bit stream from the disk drive, low active.
Each falling edge represents a flux transition of the
encoded data.
This active low high current driver allows current to
flow through the write head. It becomes active just
prior to writing to the diskette.
registers
DESCRIPTION
Used internally to qualify
section
for
additional
Rev. 02-16-07