FDC37N769_07 SMSC [SMSC Corporation], FDC37N769_07 Datasheet - Page 99

• Manufacturer Part Number: FDC37N769_07
• Description: 3.3V Super I/O Controller with Infrared Support for Portable Applications
• Manufacturer: SMSC [SMSC Corporation]

CR02
CR02 can only be accessed in the configuration state and after the CSR has been initialized to 02H. The default
value of this register after power up is 88H (Table 78).
NOTE
CR03
CR03 can only be accessed in the configuration state and after the CSR has been initialized to 03H. The default
value after power up is 70H (Table 79).
NOTE
SMSC DS – FDC37N769
1
1
: Power Down bits disable the respective logical device and associated pins, however the power down bit
: See NOTE
does not disable the selected address range for the logical device. To disable the host address registers the
logical device’s base address must be set below 100h. Devices that are powered down but still reside at a
valid I/O base address will participate in Plug-and-Play range checking.
BIT NO.
BIT NO.
0:2
4:6
7,2
3
7
0
1
3
4
5
6
2
in section CR05 on page 101.
Reserved
UART1 Power Down
Reserved
UART2 Power Down
PWRGD/
GAMECS
Enhanced Floppy
Mode 2
Reserved
DRVDEN1
MFM
IDENT
ADRx/
DRV2 EN/
IRQ_B
BIT NAME
BIT NAME
DATASHEET
1
1
Read Only. A read returns “0”.
A high level on this bit, allows normal operation of the Primary
Serial Port (Default). A low level on this bit places the Primary
Serial Port into Power Down Mode.
Read Only. A read returns “0”.
A high level on this bit, allows normal operation of the
Secondary Serial Port, including the SCE/FIR block (Default).
A low level on this bit places the Secondary Serial Port
including the SCE/FIR block into Power Down Mode.
Bit 0
Reserved - Read as zero
Bit 4
IDENT is used in conjunction with MFM to define the FDC
interface mode.
Bit - 7 Bit - 2
0
1
0
1
IDENT
Bit 1
0
1
1
Table 78 - CR02
Table 79 - CR03
0
1
1
1
0
0
Page 99 of 137
Pin Function
PWRGD (default)
GAMECS
Pin DRVDEN1 Output
Output Programmed DRVDEN1 Value
Force DRVDEN1 Output High (default)
x
0
1
Floppy Mode - Refer to the description of the TAPE
DRIVE REGISTER (TDR) for more information on
these modes.
NORMAL Floppy Mode (Default)
Enhanced Floppy Mode 2 (OS2)
MFM
1
0
1
0
Pin 92
DRV2 (Input)
ADRX
IRQ_B
DESCRIPTION
DESCRIPTION
MODE
AT Mode (Default)
Reserved
PS/2
Model 30
1
Rev. 02-16-07