FDC37N769_07 SMSC [SMSC Corporation], FDC37N769_07 Datasheet - Page 24

• Manufacturer Part Number: FDC37N769_07
• Description: 3.3V Super I/O Controller with Infrared Support for Portable Applications
• Manufacturer: SMSC [SMSC Corporation]

DATA RATE SELECT REGISTER (DSR)
The Data Rate Select Register (Base Address + 4: Write-only) is used to program the data rate, amount of write
precompensation, power down status, and software reset (Table 20). Note: the data rate is programmed using the
Configuration Control Register (CCR) not the DSR, for PC/AT and PS/2 Model 30 and Microchannel applications.
Other applications can set the data rate in the DSR. The data rate of the floppy controller is the most recent write of
either the DSR or CCR. The DSR is unaffected by a software reset. A hardware reset will set the DSR to 02H, which
corresponds to the default precompensation setting and 250 Kbps.
Data Rate Select, Bits 0 - 1
These bits control the data rate of the floppy controller. See Table 22 for the settings corresponding to the individual
data rates. The data rate select bits are unaffected by a software reset and are set to 250 Kbps after a hardware
reset.
Precompensation Select, Bits 2 - 4
These three bits select the value of write precompensation that will be applied to the WDATA output signal. Table 21
shows the precompensation values for the combination of these bits settings. Track 0 is the default starting track
number to start precompensation. The starting track number can be changed using the Configure command.
Undefined, Bit 5
Should be written as a logic “0”.
Low Power, Bit 6
A logic “1” written to this bit will put the floppy controller into Manual Low Power mode. The floppy controller clock and
data separator circuits will be turned off. The controller will come out of manual low power mode after a software
reset or following access to the Data Register or Main Status Register.
Software Reset, Bit 7
This active high bit has the same function as the DOR RESET (DOR bit 2) except that this bit is self clearing.
SMSC DS – FDC37N769
CONDITION
RESET
RESET
S/W
7
0
POWER
DOWN
Table 20 - Data Rate Select Register
6
0
DATASHEET
5
0
0
Page 24 of 137
COMP2
PRE-
4
0
COMP1
PRE-
3
0
COMP0
PRE-
2
0
DRATE
SEL1
1
1
DRATE
SEL0
0
0
Rev. 02-16-07