SAF-XE167F-48F66L INFINEON [Infineon Technologies AG], SAF-XE167F-48F66L Datasheet - Page 38

• Manufacturer Part Number: SAF-XE167F-48F66L
• Description: 16-Bit Single-Chip Real Time Signal Controller
• Manufacturer: INFINEON [Infineon Technologies AG]

3
The architecture of the XE167 combines advantages of RISC, CISC, and DSP
processors with an advanced peripheral subsystem in a well-balanced design. On-chip
memory blocks allow the design of compact systems-on-silicon with maximum
performance suited for computing, control, and communication.
The on-chip memory blocks (program code memory and SRAM, dual-port RAM, data
SRAM) and the generic peripherals are connected to the CPU by separate high-speed
buses. Another bus, the LXBus, connects additional on-chip resources and external
resources (see
enabling the concurrent operation of several subsystems of the XE167.
The block diagram gives an overview of the on-chip components and the advanced
internal bus structure of the XE167.
Figure 3
Data Sheet
ADC1
10-Bit
8-Bit/
8 Ch.
P15
Clock, Reset, Power Control,
Program Flash 0
Program Flash 1
Program Flash 2
16/32/64 Kbytes
0/64/256 Kbytes
128/256 Kbytes
8
Functional Description
256 Kbytes
System Functions
PSRAM
Block Diagram
16 Ch.
Stand-By RAM
ADC0
10-Bit
8-Bit/
Figure
Port 5
16
BRGen
GPT
T2
T3
T4
T5
T6
3). This bus structure enhances overall system performance by
P11
6
CC2
T7
T8
P10
2 Kbytes
CCU63
DPRAM
T12
T13
16
Interrupt Bus
C166SV2 - Core
...
P9
Interrupt & PEC
8
CCU60
CPU
36
T12
T13
P8
7
16 Kbytes
P7 P6
DSRAM
5
4
USIC2
RS232,
IIC, IIS
2 Ch.,
Buffer
64 x
LIN,
SPI,
P4
8
XE166 Family Derivatives
USIC1
RS232,
IIC, IIS
2 Ch.,
Buffer
P3
64 x
LIN,
SPI,
8
Functional Description
MC_XE167X_BLOCKDIAGRAM
USIC0
RS232,
IIC, IIS
2 Ch.,
Buffer
P2
64 x
LIN,
SPI,
WDT
RTC
13
Debug Support
LXBus Control
External Bus
Control
OCDS
EBC
2/5ch.
P1
Multi
CAN
8
V2.1, 2008-08
P0
XE167x
8