SAF-XE167F-48F66L INFINEON [Infineon Technologies AG], SAF-XE167F-48F66L Datasheet - Page 39

• Manufacturer Part Number: SAF-XE167F-48F66L
• Description: 16-Bit Single-Chip Real Time Signal Controller
• Manufacturer: INFINEON [Infineon Technologies AG]

3.1
The memory space of the XE167 is configured in the von Neumann architecture. In this
architecture all internal and external resources, including code memory, data memory,
registers and I/O ports, are organized in the same linear address space.
Table 5
Address Area
IMB register space
Reserved (Access trap) F0’0000
Reserved for EPSRAM E9’0000
Emulated PSRAM
Reserved for PSRAM
Program SRAM
Reserved for pr. mem.
Program Flash 2
Program Flash 1
Program Flash 0
External memory area
Available Ext. IO area
USIC registers
MultiCAN registers
External memory area
SFR area
Dual-Port RAM
Reserved for DPRAM
ESFR area
XSFR area
Data SRAM
Reserved for DSRAM
External memory area
1) The areas marked with “<” are slightly smaller than indicated. See column “Notes”.
2) The uppermost 4-Kbyte sector of the first Flash segment is reserved for internal use (C0’F000
3) Several pipeline optimizations are not active within the external IO area. This is necessary to control external
Data Sheet
peripherals properly.
Memory Subsystem and Organization
XE167 Memory Map
3)
Start Loc.
FF’FF00
E8’0000
E1’0000
E0’0000
CC’0000
C8’0000
C4’0000
C0’0000
40’0000
20’5800
20’4000
20’0000
01’0000
00’FE00
00’F600
00’F200
00’F000
00’E000
00’A000
00’8000
00’0000
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
End Loc.
FF’FFFF
FF’FEFF
EF’FFFF
E8’FFFF
E7’FFFF
E0’FFFF
DF’FFFF
CB’FFFF
C7’FFFF
C3’FFFF
BF’FFFF
3F’FFFF
20’57FF
20’3FFF
1F’FFFF
00’FFFF
00’FDFF
00’F5FF
00’F1FF
00’EFFF
00’DFFF
00’9FFF
00’7FFF
37
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
Area Size
256 Bytes
<1 Mbyte
448 Kbytes
64 Kbytes
448 Kbytes
64 Kbytes
<1.25 Mbytes –
256 Kbytes
256 Kbytes
256 Kbytes
8 Mbytes
< 2 Mbytes
6 Kbytes
16 Kbytes
< 2 Mbytes
0.5 Kbyte
2 Kbytes
1 Kbyte
0.5 Kbyte
4 Kbytes
16 Kbytes
8 Kbytes
32 Kbytes
XE166 Family Derivatives
1)
Functional Description
Notes
–
Minus IMB registers
Mirrors EPSRAM
Flash timing
Mirrors PSRAM
Maximum speed
–
–
2)
–
Minus USIC/CAN
Accessed via EBC
Accessed via EBC
Minus segment 0
–
–
–
–
–
–
–
–
V2.1, 2008-08
H
to C0’FFFF
XE167x
H
).