SAK-XC161CJ-16F20F INFINEON [Infineon Technologies AG], SAK-XC161CJ-16F20F Datasheet - Page 64

• Manufacturer Part Number: SAK-XC161CJ-16F20F
• Description: 16-Bi t Single-Chip Microcontroller Preliminary
• Manufacturer: INFINEON [Infineon Technologies AG]

Preliminary
Bypass Operation
When bypass operation is configured (PLLCTRL = 0x
the internal oscillator (input clock signal XTAL1) through the input- and output-
prescalers:
f
If both divider factors are selected as ’1’ (PLLIDIV = PLLODIV = ’0’) the frequency of
directly follows the frequency of
duty cycle of the input clock
The lowest master clock frequency is achieved by selecting the maximum values for both
divider factors:
f
Phase Locked Loop (PLL)
When PLL operation is configured (PLLCTRL = 11
enabled and provides the master clock. The PLL multiplies the input frequency by the
factor F (
and the output divider (F = PLLMUL+1 / (PLLIDIV+1
synchronizes the master clock to the input clock. This synchronization is done smoothly,
i.e. the master clock frequency does not change abruptly.
Due to this adaptation to the input clock the frequency of
is locked to
of individual TCMs.
The timing listed in the AC Characteristics refers to TCPs. Because
f
circumstances.
The actual minimum value for TCP depends on the jitter of the PLL. As the PLL is
constantly adjusting its output frequency so it corresponds to the applied input frequency
(crystal or oscillator) the relative deviation for periods of more than one TCP is lower than
for one single TCP.
This is especially important for bus cycles using waitstates and e.g. for the operation of
timers, serial interfaces, etc. For all slower operations and longer periods (e.g. pulse train
generation or measurement, lower baudrates, etc.) the deviation caused by the PLL jitter
is negligible.
Data Sheet
MC
MC
MC
, the timing must be calculated using the minimum TCP possible under the respective
=
=
f
f
OSC
OSC
f
MC
/ ((PLLIDIV+1) (PLLODIV+1)).
/ ((3+1) (14+1)) =
f
OSC
=
f
. The slight variation causes a jitter of
OSC
F) which results from the input divider, the multiplication factor,
f
OSC
f
OSC
f
.
OSC
/ 60.
so the high and low time of
60
B
) the on-chip phase locked loop is
B
f
MC
) the master clock is derived from
PLLODIV+1)). The PLL circuit
f
which also affects the duration
MC
is constantly adjusted so it
f
Timing Parameters
MC
f
CPU
is defined by the
is derived from
Derivatives
V1.0, 2002-03
XC161
f
MC